PR to update the tutorial Makefiles

[jaimebw]

Hi Obijuan,
First of all, thanks for the awesome tutorial. It is really helping me start my (open-source) journey with FPGAs.
I don't know if you would be interested in updating some of the Makefiles/docs for some updated resources.
Mainly, arachne-pnr is no longer supported, so I have been updating everything to use a nextpnr.
I can definitely try to push the changes once I've gone through the whole tutorial.

[jaimebw]

The main changes are like from this:

open-fpga-verilog-tutorial/tutorial/ICE40-HX8K_Breakout_Board/T03-inv/Makefile

Lines 34 to 42 in b138902

	#-- Compilar
	iverilog $^ -o $(NAME)_tb.out
	#-- Simular
	./$(NAME)_tb.out
	#-- Ver visualmente la simulacion con gtkwave
	gtkwave $@ $(NAME)_tb.gtkw &

To something like this:

	#-- Compilar
	iverilog -o $(NAME)_tb.out $(NAME)_tb.v $(NAME).v
	#-- Simular
	./$(NAME)_tb.out
	
	#-- Ver visualmente la simulacion con gtkwave
	gtkwave $@ $(NAME)_tb.gtkw &

Same here:

open-fpga-verilog-tutorial/tutorial/ICE40-HX8K_Breakout_Board/T03-inv/Makefile

Lines 46 to 55 in b138902

	$(NAME).bin: $(NAME).pcf $(NAME).v
	#-- Sintesis
	yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v
	#-- Place & route
	arachne-pnr -d 8k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt
	#-- Generar binario final, listo para descargar en fgpa
	icepack $(NAME).txt $(NAME).bin

To something like this:

	#-- Sintesis
	yosys -p "synth_ice40 -top $(NAME) -json $(NAME).json" $(NAME).v
	
	#-- Place & route

	nextpnr-ice40 --lp1k --json $(NAME).json --pcf $(NAME).pcf --asc $(NAME).asc
	#-- Generar binario final, listo para descargar en fgpa
	icepack $(NAME).asc $(NAME).bin

I'm currently running under MacOs.

Also, there are some issues when I compile Verilog. Mainly, it has to do with re-declaring wires like in:

open-fpga-verilog-tutorial/tutorial/ICE40-HX8K_Breakout_Board/T02-Fport/Fport.v

Lines 16 to 27 in b138902

	module Fport(output [3:0] data);
	//-- La salida del modulo son 4 cables
	wire [3:0] data;
	//-- Sacar el valor por el bus de salida
	//-- En verilog se indica primero el numero de bits
	//-- y luego el formato (binario, hexa, decimal, etc...)
	//-- Para sacar el valor en hexa hay que poner: 4'h4
	assign data = 4'b1010; //-- 4'hA
	endmodule

It complains and I have read that the newer standards do not let you declare explicitly that way. Corrected (more like more correct example):

odule Fport(output [3:0] data);

  //-- La salida del modulo son 4 cables
  //wire [3:0] data;

  //-- Sacar el valor por el bus de salida
  //-- En verilog se indica primero el numero de bits
  //-- y luego el formato (binario, hexa, decimal, etc...)
  //-- Para sacar el valor en hexa hay que poner: 4'h4
  assign data = 4'b1010; //-- 4'hA

endmodule