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Moved the paging documentation to the README
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‎kernel/src/memory/README.md‎

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@@ -14,3 +14,176 @@ Firefly uses the following layout of virtual memory:
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| Kernel stacks 1+ | `0xffff_8000_555d_0000` | `0xffff_8000_5d5c_ffff` | 32,768x 4 KiB page | 128 MiB |
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| MMIO address space | `0xffff_8000_6666_0000` | `0xffff_8000_6675_ffff` | 256x 4 KiB page | 1 MiB |
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| Physical memory map | `0xffff_8000_8000_0000` | `0xffff_ffff_ffff_ffff` | rest of memory | < 128 TiB |
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## Paging
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The following high-level discussion of 4-level paging may be helpful:
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Paging maps a virtual address (referred to in the Intel manuals as a 'linear address')
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to a physical address, through a series of page tables. Different parts of the virtual
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address reference different tables, as shown below:
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```
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6 5 4
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Ignored | PML4 | PDPT ~
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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~ | PDT | Table | Offset |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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Ignored: Not used during address translation.
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PML4: Used as an index into the Page Map Level 4 table (9 bits, 0-511).
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PDPT: Used as an index into the Page Directory Pointer table (9 bits, 0-511).
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PDT: Used as an index into the Page Directory table (9 bits, 0-511).
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PT: Used as an index into the Page table (9 bits, 0-511).
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Offset: Used as an index into the page (12 bits, 4kB).
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```
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A PML4 table comprises 512 64-bit entries (PML4Es)
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PML4 entry referencing a PDP entry:
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```
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6 5 4
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|X| - | PDPT Address ~
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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~ PDPT Address | - |S|-|A|C|W|U|R|P|
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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X (Execute disable): Whether the memory is executable (0) or not (1).
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- (Ignored)
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PDPT Address: The address of the entry in the Page Directory Pointer Table.
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- (Ignored)
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S (Page size): Must be 0.
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- (Ignored)
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A (Accessed): Whether the memory has been accessed (1) or not (0).
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C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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U (User): Whether the memory is accessible to userspace.
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R (Read-only): Whether the memory is read/write (1) or read-only (0).
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P (Present): Whether this entry is active (1) or absent (0).
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```
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A 4-KByte naturally aligned page-directory-pointer table is located at the
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physical address specified in bits 51:12 of the PML4E. A page-directory-pointer
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table comprises 512 64-bit entries (PDPTEs).
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PDPT entry referencing a PD entry:
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```
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6 5 4
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|X| - | PD Address ~
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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~ PD Address | - |S|-|A|C|W|U|R|P|
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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X (Execute disable): Whether the memory is executable (0) or not (1).
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- (Ignored)
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PD Address: The address of the entry in the Page Directory table.
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- (Ignored)
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S (Page size): Whether the address is for a PD entry (0) or a physical address (1).
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- (Ignored)
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A (Accessed): Whether the memory has been accessed (1) or not (0).
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C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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U (User): Whether the memory is accessible to userspace.
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R (Read-only): Whether the memory is read/write (1) or read-only (0).
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P (Present): Whether this entry is active (1) or absent (0).
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```
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Because a PDPTE is identified using bits 47:30 of the linear address, it controls
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access to a 1-GByte region of the linear-address space. Use of the PDPTE depends
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on its PS flag:
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- If the PDPTE’s PS flag is 1, the PDPTE maps a 1-GByte page.
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- If the PDPTE’s PS flag is 0, a 4-KByte naturally aligned page directory is
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located at the physical address specified in bits 51:12 of the PDPTE. A page
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directory comprises 512 64-bit entries.
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PD entry referencing a 2MB page:
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```
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6 5 4
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|X| - | PT Address ~
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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~ PT Address | - |S|-|A|C|W|U|R|P|
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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X (Execute disable): Whether the memory is executable (0) or not (1).
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- (Ignored)
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PT Address: The address of the page table.
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- (Ignored)
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S (Page size): Whether the address is for a PT entry (0) or a physical address (1).
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- (Ignored)
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A (Accessed): Whether the memory has been accessed (1) or not (0).
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C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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U (User): Whether the memory is accessible to userspace.
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R (Read-only): Whether the memory is read/write (1) or read-only (0).
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P (Present): Whether this entry is active (1) or absent (0).
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```
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Because a PDE is identified using bits 47:21 of the linear address, it
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controls access to a 2-MByte region of the linear-address space. Use of
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the PDE depends on its PS flag:
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- If the PDE's PS flag is 1, the PDE maps a 2-MByte page.
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- If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is
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located at the physical address specified in bits 51:12 of the PDE.
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A page table comprises 512 64-bit entries.
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PT entry referencing a 4kB page:
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```
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6 5 4
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3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|X| - | Page Address ~
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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3 2 1
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1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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~ Page Address | - |G|S|-|A|C|W|U|R|P|
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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X (Execute disable): Whether the memory is executable (0) or not (1).
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- (Ignored)
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PT Address: The address of the page table.
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- (Ignored)
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G (Global): Whether to flush the TLB cache when changing mappings.
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S (Page size): Whether the address is for a PT entry (0) or a physical address (1).
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D (Dirty): Whether the memory has been written (1) or not (0).
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A (Accessed): Whether the memory has been accessed (1) or not (0).
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C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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U (User): Whether the memory is accessible to userspace.
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R (Read-only): Whether the memory is read/write (1) or read-only (0).
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P (Present): Whether this entry is active (1) or absent (0).
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```
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Because a PTE is identified using bits 47:21 of the linear address, it
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controls access to a 4-kByte region of the linear-address space.

‎kernel/src/memory/mod.rs‎

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@@ -15,169 +15,6 @@
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// This crate also provides a basic physical memory frame
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// allocator, which is used in the allocator module to
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// build the memory manager.
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//
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// Although paging is covered by the x86_64 crate, the
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// following high-level discussion of 4-level paging may
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// be helpful:
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//
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// Paging maps a virtual address (referred to in the Intel manuals as a 'linear address')
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// to a physical address, through a series of page tables. Different parts of the virtual
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// address reference different tables, as shown below:
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//
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// 6 5 4
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// | Ignored | PML4 | PDPT ~
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// ~ | PDT | Table | Offset |
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// Ignored: Not used during address translation.
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// PML4: Used as an index into the Page Map Level 4 table (9 bits, 0-511).
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// PDPT: Used as an index into the Page Directory Pointer table (9 bits, 0-511).
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// PDT: Used as an index into the Page Directory table (9 bits, 0-511).
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// PT: Used as an index into the Page table (9 bits, 0-511).
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// Offset: Used as an index into the page (12 bits, 4kB).
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//
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// A PML4 table comprises 512 64-bit entries (PML4Es)
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//
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// PML4 entry referencing a PDP entry:
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//
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// 6 5 4
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// |X| - | PDPT Address ~
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// ~ PDPT Address | - |S|-|A|C|W|U|R|P|
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// X (Execute disable): Whether the memory is executable (0) or not (1).
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// - (Ignored)
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// PDPT Address: The address of the entry in the Page Directory Pointer Table.
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// - (Ignored)
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// S (Page size): Must be 0.
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// - (Ignored)
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// A (Accessed): Whether the memory has been accessed (1) or not (0).
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// C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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// W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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// U (User): Whether the memory is accessible to userspace.
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// R (Read-only): Whether the memory is read/write (1) or read-only (0).
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// P (Present): Whether this entry is active (1) or absent (0).
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//
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// A 4-KByte naturally aligned page-directory-pointer table is located at the
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// physical address specified in bits 51:12 of the PML4E. A page-directory-pointer
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// table comprises 512 64-bit entries (PDPTEs).
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//
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// PDPT entry referencing a PD entry:
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//
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// 6 5 4
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// |X| - | PD Address ~
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// ~ PD Address | - |S|-|A|C|W|U|R|P|
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// X (Execute disable): Whether the memory is executable (0) or not (1).
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// - (Ignored)
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// PD Address: The address of the entry in the Page Directory table.
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// - (Ignored)
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// S (Page size): Whether the address is for a PD entry (0) or a physical address (1).
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// - (Ignored)
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// A (Accessed): Whether the memory has been accessed (1) or not (0).
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// C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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// W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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// U (User): Whether the memory is accessible to userspace.
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// R (Read-only): Whether the memory is read/write (1) or read-only (0).
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// P (Present): Whether this entry is active (1) or absent (0).
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//
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// Because a PDPTE is identified using bits 47:30 of the linear address, it controls
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// access to a 1-GByte region of the linear-address space. Use of the PDPTE depends
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// on its PS flag:
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//
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// - If the PDPTE’s PS flag is 1, the PDPTE maps a 1-GByte page.
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// - If the PDPTE’s PS flag is 0, a 4-KByte naturally aligned page directory is
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// located at the physical address specified in bits 51:12 of the PDPTE. A page
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// directory comprises 512 64-bit entries.
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//
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// PD entry referencing a 2MB page:
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//
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// 6 5 4
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// |X| - | PT Address ~
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// ~ PT Address | - |S|-|A|C|W|U|R|P|
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// X (Execute disable): Whether the memory is executable (0) or not (1).
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// - (Ignored)
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// PT Address: The address of the page table.
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// - (Ignored)
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// S (Page size): Whether the address is for a PT entry (0) or a physical address (1).
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// - (Ignored)
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// A (Accessed): Whether the memory has been accessed (1) or not (0).
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// C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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// W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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// U (User): Whether the memory is accessible to userspace.
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// R (Read-only): Whether the memory is read/write (1) or read-only (0).
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// P (Present): Whether this entry is active (1) or absent (0).
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//
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// Because a PDE is identified using bits 47:21 of the linear address, it
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// controls access to a 2-MByte region of the linear-address space. Use of
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// the PDE depends on its PS flag:
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//
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// - If the PDE's PS flag is 1, the PDE maps a 2-MByte page.
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// - If the PDE’s PS flag is 0, a 4-KByte naturally aligned page table is
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// located at the physical address specified in bits 51:12 of the PDE.
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// A page table comprises 512 64-bit entries.
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//
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// PT entry referencing a 4kB page:
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//
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// 6 5 4
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// |X| - | Page Address ~
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// 3 2 1
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// 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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// ~ Page Address | - |G|S|-|A|C|W|U|R|P|
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// +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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//
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// X (Execute disable): Whether the memory is executable (0) or not (1).
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// - (Ignored)
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// PT Address: The address of the page table.
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// - (Ignored)
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// G (Global): Whether to flush the TLB cache when changing mappings.
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// S (Page size): Whether the address is for a PT entry (0) or a physical address (1).
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// D (Dirty): Whether the memory has been written (1) or not (0).
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// A (Accessed): Whether the memory has been accessed (1) or not (0).
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// C (Cache disable): Whether the memory has caching enabled (0) or disabled (1).
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// W (Write-through): Whether the memory has write-through caching (1) or write-back (0).
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// U (User): Whether the memory is accessible to userspace.
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// R (Read-only): Whether the memory is read/write (1) or read-only (0).
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// P (Present): Whether this entry is active (1) or absent (0).
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//
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// Because a PTE is identified using bits 47:21 of the linear address, it
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// controls access to a 4-kByte region of the linear-address space.
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use bootloader::BootInfo;
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use x86_64::registers::control::Cr3;

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