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Changed Statement to Instruction
1 parent 17fbe28 commit 88fe213

2 files changed

Lines changed: 76 additions & 73 deletions

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‎src/main/kotlin/deep/decaf/low/CFG.kt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
package deep.decaf.low
22

33
import deep.decaf.ir.*
4-
import java.lang.RuntimeException
54
import java.util.*
65

76
interface CFGNode {

‎src/main/kotlin/deep/decaf/low/amd64/LowIRClasses.kt‎

Lines changed: 76 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -116,114 +116,114 @@ enum class SetType {
116116
}
117117
}
118118

119-
sealed class Statement
120-
data class AddStatement(val src: Location, val dest: Location) : Statement() {
119+
sealed class Instruction
120+
data class AddInstruction(val src: Location, val dest: Location) : Instruction() {
121121
override fun toString(): String {
122122
return "add $src, $dest"
123123
}
124124
}
125125

126-
data class SubStatement(val src: Location, val dest: Location) : Statement() {
126+
data class SubInstruction(val src: Location, val dest: Location) : Instruction() {
127127
override fun toString(): String {
128128
return "sub $src, $dest"
129129
}
130130
}
131131

132-
data class IMulStatement(val src: Location, val dest: Location) : Statement() {
132+
data class IMulInstruction(val src: Location, val dest: Location) : Instruction() {
133133
override fun toString(): String {
134134
return "imul $src, $dest"
135135
}
136136
}
137137

138-
data class IDivStatement(val src: Location) : Statement() {
138+
data class IDivInstruction(val src: Location) : Instruction() {
139139
override fun toString(): String {
140140
return "idivq $src"
141141
}
142142
}
143143

144-
data class CmpStatement(val src: Location, val dest: Location) : Statement() {
144+
data class CmpInstruction(val src: Location, val dest: Location) : Instruction() {
145145
override fun toString(): String {
146146
return "cmp $src, $dest"
147147
}
148148
}
149149

150-
data class AndStatement(val src: Location, val dest: Location) : Statement() {
150+
data class AndInstruction(val src: Location, val dest: Location) : Instruction() {
151151
override fun toString(): String {
152152
return "and $src, $dest"
153153
}
154154
}
155155

156-
data class OrStatement(val src: Location, val dest: Location) : Statement() {
156+
data class OrInstruction(val src: Location, val dest: Location) : Instruction() {
157157
override fun toString(): String {
158158
return "or $src, $dest"
159159
}
160160
}
161161

162-
data class NotStatement(val src: Location) : Statement() {
162+
data class NotInstruction(val src: Location) : Instruction() {
163163
override fun toString(): String {
164164
return "not $src"
165165
}
166166
}
167167

168-
data class NegStatement(val src: Location) : Statement() {
168+
data class NegInstruction(val src: Location) : Instruction() {
169169
override fun toString(): String {
170170
return "nge $src"
171171
}
172172
}
173173

174-
data class JumpStatement(val type: AsmJumpOp, val target: String) : Statement() {
174+
data class JumpInstruction(val type: AsmJumpOp, val target: String) : Instruction() {
175175
override fun toString(): String {
176176
return "$type $target"
177177
}
178178
}
179179

180-
data class MoveStatement(val src: Location, val dest: Location) : Statement() {
180+
data class MoveInstruction(val src: Location, val dest: Location) : Instruction() {
181181
override fun toString(): String {
182182
return "mov $src, $dest"
183183
}
184184
}
185185

186-
data class CMoveStatement(val type: AsmCMoveOp, val src: Register, val dest: Register) : Statement() {
186+
data class CMoveInstruction(val type: AsmCMoveOp, val src: Register, val dest: Register) : Instruction() {
187187
override fun toString(): String {
188188
return "$type $src $dest"
189189
}
190190
}
191191

192-
data class SetStatement(val type: SetType, val reg: Register) : Statement() {
192+
data class SetInstruction(val type: SetType, val reg: Register) : Instruction() {
193193
override fun toString(): String {
194194
return "$type $reg"
195195
}
196196
}
197197

198-
object SignedExtendStatement : Statement() {
198+
object SignedExtendInstruction : Instruction() {
199199
override fun toString() = "cqto"
200200
}
201201

202-
object ReturnStatement : Statement() {
202+
object ReturnInstruction : Instruction() {
203203
override fun toString() = "ret"
204204
}
205205

206-
data class CallStatement(val label: String) : Statement() {
206+
data class CallInstruction(val label: String) : Instruction() {
207207
override fun toString() = "call $label"
208208
}
209209

210-
data class PushStatement(val src: Location) : Statement() {
210+
data class PushInstruction(val src: Location) : Instruction() {
211211
override fun toString() = "push $src"
212212
}
213213

214-
data class PopStatement(val src: Location?) : Statement() {
214+
data class PopInstruction(val src: Location?) : Instruction() {
215215
override fun toString() = "pop ${src ?: ""}"
216216
}
217217

218-
object LeaveStatement : Statement() {
218+
object LeaveInstruction : Instruction() {
219219
override fun toString() = "leave"
220220
}
221221

222-
data class EnterStatement(val size: ImmediateVal) : Statement() {
222+
data class EnterInstruction(val size: ImmediateVal) : Instruction() {
223223
override fun toString() = "enter \$($size*8), $0"
224224
}
225225

226-
data class Block(val label: String?, val statements: List<Statement>)
226+
data class Block(val label: String?, val instructions: List<Instruction>)
227227

228228
data class Method(
229229
var stackSize: Int,
@@ -239,115 +239,115 @@ data class Program(
239239
var methods: List<Method>
240240
)
241241

242-
fun irExprToLow(expr: IRExpr): List<Statement> {
243-
val statements = mutableListOf<Statement>()
242+
fun irExprToLow(expr: IRExpr): List<Instruction> {
243+
val statements = mutableListOf<Instruction>()
244244

245245
fun traverse(expr: IRExpr): Location {
246246
return when (expr) {
247247
is IRIntLiteral -> ImmediateVal(expr.lit)
248248
is IRBoolLiteral -> ImmediateVal(if (expr.lit) 1 else 0)
249249
is IRMethodCallExpr -> {
250250
val argLocations = expr.argList.map { traverse(it) }
251-
argLocations.forEach { statements.add(PushStatement(it)) }
252-
statements.add(CallStatement(expr.name))
251+
argLocations.forEach { statements.add(PushInstruction(it)) }
252+
statements.add(CallInstruction(expr.name))
253253
for (i in 1..expr.argList.size) {
254-
statements.add(PopStatement(null))
254+
statements.add(PopInstruction(null))
255255
}
256256
Register.returnRegister()
257257
}
258258
is IRCallOutExpr -> TODO()
259259
is IRBinOpExpr -> {
260260
val leftLocation = traverse(expr.left)
261261
val rightLocation = traverse(expr.right)
262-
statements.add(MoveStatement(leftLocation, Register.r10()))
263-
statements.add(MoveStatement(rightLocation, Register.r11()))
262+
statements.add(MoveInstruction(leftLocation, Register.r10()))
263+
statements.add(MoveInstruction(rightLocation, Register.r11()))
264264
when (expr.op) {
265265
BinOp.ADD -> {
266-
statements.add(AddStatement(Register.r11(), Register.r10()))
266+
statements.add(AddInstruction(Register.r11(), Register.r10()))
267267
val tmp = Label(getUUID())
268-
statements.add(MoveStatement(Register.r10(), tmp))
268+
statements.add(MoveInstruction(Register.r10(), tmp))
269269
tmp
270270
}
271271
BinOp.SUBTRACT -> {
272-
statements.add(SubStatement(Register.r11(), Register.r10()))
272+
statements.add(SubInstruction(Register.r11(), Register.r10()))
273273
val tmp = Label(getUUID())
274-
statements.add(MoveStatement(Register.r10(), tmp))
274+
statements.add(MoveInstruction(Register.r10(), tmp))
275275
tmp
276276
}
277277
BinOp.MULTIPLY -> {
278-
statements.add(IMulStatement(Register.r11(), Register.r10()))
278+
statements.add(IMulInstruction(Register.r11(), Register.r10()))
279279
val tmp = Label(getUUID())
280-
statements.add(MoveStatement(Register.r10(), tmp))
280+
statements.add(MoveInstruction(Register.r10(), tmp))
281281
tmp
282282
}
283283
BinOp.DIVIDE -> {
284-
statements.add(MoveStatement(Register.r10(), Register.rax()))
285-
statements.add(SignedExtendStatement)
286-
statements.add(IDivStatement(Register.r11()))
284+
statements.add(MoveInstruction(Register.r10(), Register.rax()))
285+
statements.add(SignedExtendInstruction)
286+
statements.add(IDivInstruction(Register.r11()))
287287
val tmp = Label(getUUID())
288-
statements.add(MoveStatement(Register.rax(), tmp))
288+
statements.add(MoveInstruction(Register.rax(), tmp))
289289
tmp
290290
}
291291
BinOp.REMAINDER -> {
292-
statements.add(MoveStatement(Register.r10(), Register.rax()))
293-
statements.add(SignedExtendStatement)
294-
statements.add(IDivStatement(Register.r11()))
292+
statements.add(MoveInstruction(Register.r10(), Register.rax()))
293+
statements.add(SignedExtendInstruction)
294+
statements.add(IDivInstruction(Register.r11()))
295295
val tmp = Label(getUUID())
296-
statements.add(MoveStatement(Register.rdx(), tmp))
296+
statements.add(MoveInstruction(Register.rdx(), tmp))
297297
tmp
298298
}
299299
BinOp.LESS -> {
300-
statements.add(CmpStatement(Register.r11(), Register.r10()))
301-
statements.add(SetStatement(SetType.SETL, Register.r10b()))
300+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
301+
statements.add(SetInstruction(SetType.SETL, Register.r10b()))
302302
val tmp = Label(getUUID())
303-
statements.add(MoveStatement(Register.r10(), tmp))
303+
statements.add(MoveInstruction(Register.r10(), tmp))
304304
tmp
305305
}
306306
BinOp.MORE -> {
307-
statements.add(CmpStatement(Register.r11(), Register.r10()))
308-
statements.add(SetStatement(SetType.SETG, Register.r10b()))
307+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
308+
statements.add(SetInstruction(SetType.SETG, Register.r10b()))
309309
val tmp = Label(getUUID())
310-
statements.add(MoveStatement(Register.r10(), tmp))
310+
statements.add(MoveInstruction(Register.r10(), tmp))
311311
tmp
312312
}
313313
BinOp.LESS_OR_EQ -> {
314-
statements.add(CmpStatement(Register.r11(), Register.r10()))
315-
statements.add(SetStatement(SetType.SETLE, Register.r10b()))
314+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
315+
statements.add(SetInstruction(SetType.SETLE, Register.r10b()))
316316
val tmp = Label(getUUID())
317-
statements.add(MoveStatement(Register.r10(), tmp))
317+
statements.add(MoveInstruction(Register.r10(), tmp))
318318
tmp
319319
}
320320
BinOp.MORE_OR_EQ -> {
321-
statements.add(CmpStatement(Register.r11(), Register.r10()))
322-
statements.add(SetStatement(SetType.SETGE, Register.r10b()))
321+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
322+
statements.add(SetInstruction(SetType.SETGE, Register.r10b()))
323323
val tmp = Label(getUUID())
324-
statements.add(MoveStatement(Register.r10(), tmp))
324+
statements.add(MoveInstruction(Register.r10(), tmp))
325325
tmp
326326
}
327327
BinOp.EQ -> {
328-
statements.add(CmpStatement(Register.r11(), Register.r10()))
329-
statements.add(SetStatement(SetType.SETE, Register.r10b()))
328+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
329+
statements.add(SetInstruction(SetType.SETE, Register.r10b()))
330330
val tmp = Label(getUUID())
331-
statements.add(MoveStatement(Register.r10(), tmp))
331+
statements.add(MoveInstruction(Register.r10(), tmp))
332332
tmp
333333
}
334334
BinOp.NOT_EQ -> {
335-
statements.add(CmpStatement(Register.r11(), Register.r10()))
336-
statements.add(SetStatement(SetType.SETNE, Register.r10b()))
335+
statements.add(CmpInstruction(Register.r11(), Register.r10()))
336+
statements.add(SetInstruction(SetType.SETNE, Register.r10b()))
337337
val tmp = Label(getUUID())
338-
statements.add(MoveStatement(Register.r10(), tmp))
338+
statements.add(MoveInstruction(Register.r10(), tmp))
339339
tmp
340340
}
341341
BinOp.AND -> {
342-
statements.add(AndStatement(Register.r10(), Register.r11()))
342+
statements.add(AndInstruction(Register.r10(), Register.r11()))
343343
val tmp = Label(getUUID())
344-
statements.add(MoveStatement(Register.r11(), tmp))
344+
statements.add(MoveInstruction(Register.r11(), tmp))
345345
tmp
346346
}
347347
BinOp.OR -> {
348-
statements.add(OrStatement(Register.r10(), Register.r11()))
348+
statements.add(OrInstruction(Register.r10(), Register.r11()))
349349
val tmp = Label(getUUID())
350-
statements.add(MoveStatement(Register.r11(), tmp))
350+
statements.add(MoveInstruction(Register.r11(), tmp))
351351
tmp
352352
}
353353
}
@@ -356,17 +356,17 @@ fun irExprToLow(expr: IRExpr): List<Statement> {
356356
val loc = traverse(expr.expr)
357357
when (expr.op) {
358358
UnaryOp.MINUS -> {
359-
statements.add(MoveStatement(loc, Register.r10()))
360-
statements.add(NegStatement(Register.r10()))
359+
statements.add(MoveInstruction(loc, Register.r10()))
360+
statements.add(NegInstruction(Register.r10()))
361361
val tmp = Label(getUUID())
362-
statements.add(MoveStatement(Register.r10(), tmp))
362+
statements.add(MoveInstruction(Register.r10(), tmp))
363363
tmp
364364
}
365365
UnaryOp.NOT -> {
366-
statements.add(MoveStatement(loc, Register.r10()))
367-
statements.add(NotStatement(Register.r10b()))
366+
statements.add(MoveInstruction(loc, Register.r10()))
367+
statements.add(NotInstruction(Register.r10b()))
368368
val tmp = Label(getUUID())
369-
statements.add(MoveStatement(Register.r10(), tmp))
369+
statements.add(MoveInstruction(Register.r10(), tmp))
370370
tmp
371371
}
372372
}
@@ -376,7 +376,7 @@ fun irExprToLow(expr: IRExpr): List<Statement> {
376376
is IRIDLocation -> Label(location.name)
377377
is IRArrayLocation -> {
378378
val index = traverse(location.indexExpr)
379-
statements.add(MoveStatement(index, Register.r10()))
379+
statements.add(MoveInstruction(index, Register.r10()))
380380
ArrayAsm(location.name, Register.r10())
381381
}
382382
}
@@ -386,4 +386,8 @@ fun irExprToLow(expr: IRExpr): List<Statement> {
386386

387387
traverse(expr)
388388
return statements
389+
}
390+
391+
fun irStatementToLower(statements: IRStatement) {
392+
389393
}

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