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Completed IRExpr to Low translation
1 parent bd5c053 commit a45c69f

1 file changed

Lines changed: 106 additions & 16 deletions

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‎src/main/kotlin/deep/decaf/low/amd64/LowIRClasses.kt‎

Lines changed: 106 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ fun getUUID(): String = UUID.randomUUID().toString().replace("-", "")
88
sealed class Offset
99
data class NumberOffset(val offset: Int) : Offset()
1010
data class StringOffset(val name: String) : Offset()
11-
data class ArrayOffset(val name: String, val offsetRegister: Register) : Offset()
11+
1212

1313
sealed class Location
1414
data class ImmediateVal(val num: Int) : Location()
@@ -28,6 +28,7 @@ data class Register(val name: String, val offset: Offset?) : Location() {
2828

2929
data class Label(val label: String) : Location()
3030
data class MemLoc(val reg: Register, val offset: NumberOffset) : Location()
31+
data class ArrayAsm(val name: String, val offsetRegister: Register) : Location()
3132

3233
enum class AsmCMoveOp {
3334
CMOVE,
@@ -44,14 +45,29 @@ enum class AsmJumpOp {
4445
JNE
4546
}
4647

48+
enum class SetType {
49+
SETE,
50+
SETNE,
51+
SETG,
52+
SETL,
53+
SETGE,
54+
SETLE
55+
}
56+
4757
sealed class Statement
4858
data class AddStatement(val src: Location, val dest: Location) : Statement()
4959
data class SubStatement(val src: Location, val dest: Location) : Statement()
5060
data class IMulStatement(val src: Location, val dest: Location) : Statement()
5161
data class IDivStatement(val src: Location) : Statement()
62+
data class CmpStatement(val src: Location, val dest: Location) : Statement()
63+
data class AndStatement(val src: Location, val dest: Location): Statement()
64+
data class OrStatement(val src: Location, val dest: Location): Statement()
65+
data class NotStatement(val src: Location) : Statement()
66+
data class NegStatement(val src: Location) : Statement()
5267
data class JumpStatement(val type: AsmJumpOp, val target: String) : Statement()
5368
data class MoveStatement(val src: Location, val dest: Location) : Statement()
5469
data class CMoveStatement(val type: AsmCMoveOp, val src: Register, val dest: Register) : Statement()
70+
data class SetStatement(val type: SetType, val reg: Register) : Statement()
5571
object SignedExtendStatement : Statement()
5672
object ReturnStatement : Statement()
5773
data class CallStatement(val label: String) : Statement()
@@ -76,16 +92,16 @@ data class Program(
7692
var methods: List<Method>
7793
)
7894

79-
fun irBinOpExprToLow(expr: IRBinOpExpr): List<Statement> {
95+
fun irExprToLow(expr: IRExpr): List<Statement> {
8096
val statements = mutableListOf<Statement>()
8197

82-
fun traverse(expr: IRExpr): Location? {
98+
fun traverse(expr: IRExpr): Location {
8399
return when (expr) {
84100
is IRIntLiteral -> ImmediateVal(expr.lit)
85101
is IRBoolLiteral -> ImmediateVal(if (expr.lit) 1 else 0)
86102
is IRMethodCallExpr -> {
87103
val argLocations = expr.argList.map { traverse(it) }
88-
argLocations.forEach { statements.add(PushStatement(it!!)) }
104+
argLocations.forEach { statements.add(PushStatement(it)) }
89105
statements.add(CallStatement(expr.name))
90106
for (i in 1..expr.argList.size) {
91107
statements.add(PopStatement(null))
@@ -96,8 +112,8 @@ fun irBinOpExprToLow(expr: IRBinOpExpr): List<Statement> {
96112
is IRBinOpExpr -> {
97113
val leftLocation = traverse(expr.left)
98114
val rightLocation = traverse(expr.right)
99-
statements.add(MoveStatement(leftLocation!!, Register.r10()))
100-
statements.add(MoveStatement(rightLocation!!, Register.r11()))
115+
statements.add(MoveStatement(leftLocation, Register.r10()))
116+
statements.add(MoveStatement(rightLocation, Register.r11()))
101117
when (expr.op) {
102118
BinOp.ADD -> {
103119
statements.add(AddStatement(Register.r11(), Register.r10()))
@@ -133,20 +149,94 @@ fun irBinOpExprToLow(expr: IRBinOpExpr): List<Statement> {
133149
statements.add(MoveStatement(Register.rdx(), tmp))
134150
tmp
135151
}
136-
BinOp.LESS -> TODO()
137-
BinOp.MORE -> TODO()
138-
BinOp.LESS_OR_EQ -> TODO()
139-
BinOp.MORE_OR_EQ -> TODO()
140-
BinOp.EQ -> TODO()
141-
BinOp.NOT_EQ -> TODO()
142-
BinOp.AND -> TODO()
143-
BinOp.OR -> TODO()
152+
BinOp.LESS -> {
153+
statements.add(CmpStatement(Register.r11(), Register.r10()))
154+
statements.add(SetStatement(SetType.SETL, Register.r10b()))
155+
val tmp = Label(getUUID())
156+
statements.add(MoveStatement(Register.r10(), tmp))
157+
tmp
158+
}
159+
BinOp.MORE -> {
160+
statements.add(CmpStatement(Register.r11(), Register.r10()))
161+
statements.add(SetStatement(SetType.SETG, Register.r10b()))
162+
val tmp = Label(getUUID())
163+
statements.add(MoveStatement(Register.r10(), tmp))
164+
tmp
165+
}
166+
BinOp.LESS_OR_EQ -> {
167+
statements.add(CmpStatement(Register.r11(), Register.r10()))
168+
statements.add(SetStatement(SetType.SETLE, Register.r10b()))
169+
val tmp = Label(getUUID())
170+
statements.add(MoveStatement(Register.r10(), tmp))
171+
tmp
172+
}
173+
BinOp.MORE_OR_EQ -> {
174+
statements.add(CmpStatement(Register.r11(), Register.r10()))
175+
statements.add(SetStatement(SetType.SETGE, Register.r10b()))
176+
val tmp = Label(getUUID())
177+
statements.add(MoveStatement(Register.r10(), tmp))
178+
tmp
179+
}
180+
BinOp.EQ -> {
181+
statements.add(CmpStatement(Register.r11(), Register.r10()))
182+
statements.add(SetStatement(SetType.SETE, Register.r10b()))
183+
val tmp = Label(getUUID())
184+
statements.add(MoveStatement(Register.r10(), tmp))
185+
tmp
186+
}
187+
BinOp.NOT_EQ -> {
188+
statements.add(CmpStatement(Register.r11(), Register.r10()))
189+
statements.add(SetStatement(SetType.SETNE, Register.r10b()))
190+
val tmp = Label(getUUID())
191+
statements.add(MoveStatement(Register.r10(), tmp))
192+
tmp
193+
}
194+
BinOp.AND -> {
195+
statements.add(AndStatement(Register.r10(), Register.r11()))
196+
val tmp = Label(getUUID())
197+
statements.add(MoveStatement(Register.r11(), tmp))
198+
tmp
199+
}
200+
BinOp.OR -> {
201+
statements.add(OrStatement(Register.r10(), Register.r11()))
202+
val tmp = Label(getUUID())
203+
statements.add(MoveStatement(Register.r11(), tmp))
204+
tmp
205+
}
206+
}
207+
}
208+
is IRUnaryOpExpr -> {
209+
val loc = traverse(expr.expr)
210+
when (expr.op) {
211+
UnaryOp.MINUS -> {
212+
statements.add(MoveStatement(loc, Register.r10()))
213+
statements.add(NegStatement(Register.r10()))
214+
val tmp = Label(getUUID())
215+
statements.add(MoveStatement(Register.r10(), tmp))
216+
tmp
217+
}
218+
UnaryOp.NOT -> {
219+
statements.add(MoveStatement(loc, Register.r10()))
220+
statements.add(NotStatement(Register.r10b()))
221+
val tmp = Label(getUUID())
222+
statements.add(MoveStatement(Register.r10(), tmp))
223+
tmp
224+
}
225+
}
226+
}
227+
is IRLocationExpression -> {
228+
when (val location = expr.location) {
229+
is IRIDLocation -> Label(location.name)
230+
is IRArrayLocation -> {
231+
val index = traverse(location.indexExpr)
232+
statements.add(MoveStatement(index, Register.r10()))
233+
ArrayAsm(location.name, Register.r10())
234+
}
144235
}
145236
}
146-
is IRUnaryOpExpr -> TODO()
147-
is IRLocationExpression -> TODO()
148237
}
149238
}
150239

240+
traverse(expr)
151241
return statements
152242
}

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