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‎11_Modell_CPU.md‎

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```text @plantUML.png
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@startuml
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ditaa
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15
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15 14 0
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+-------+------------------------------------+
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|cF00 V | cFF0 |
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+-------+------------------------------------+
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+-----------------------------------------------------------------+
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@enduml
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```
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## Taktvorgabe
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```text @plantUML.png
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@startuml
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ditaa
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Zykluszeit des Speichers
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RUN/HLT 3 Bit |<-------------->|
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| Zähler +---+
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| +---+ +---+ | | +-+ +-
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+-------+ +->| | | Q+-->| +--> -+ +--------------+
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| | | & +-->|T | | |
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| +-+ +--->| | | | | | +-+
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| | | | +---+ |---| | +--> ---+ +--------------
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| -+ +- | | Q+-->| |
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| | | | | | +-+
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+-------+ | | | +--> ------+ +-----------
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Oscillator |---| | |
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| Q+-->| | +-+
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| | | +--> --------+ +---------
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| | | |
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+---+ | | +-+
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| +--> ----------+ +-------
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| |
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| | +-+
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| +--> ------------+ +-----
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| |
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| | +-+
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| +--> --------------+ +---
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| |
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| | +-+
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| +--> ----------------+ +-
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| |
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+---+
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3 zu 8 Decoder
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@enduml
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```
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## Integrierung der Taktvorgabe in Steuerwerk
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```text @plantUML.png
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@startuml
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ditaa
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Instruction Register
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+---------+------------+
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|OPCODE | |
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+-+-+-+-+-+------------+
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| | | |
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V V V V
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+-----------------------------------------------------------------+
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| 1 aus 16 Dekodierer |
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| |
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Benutzer +--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+
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Eingaben +---+ | | | | | | | | | | | | | | | |
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HLT----->| OR|<-----------------+ | | | | | | | | | | | | | | | |
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RUN----+ +-+-+ | HLT JMA JMP SRJ CSA RAL INP OUT NOT LDA STA ADD XOR IOR AND NOP
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| | | | | | | | | | | | | | | | | | |
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V V Status FF | V V V V V V V V V V V V V V V V
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+-------+ +---+ +---+ | ++----------------------------------------------------------------+ Steuersignale:
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| R | H | | F | | E |<-+ +-+HLT |
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+-+-----+ ++--+ +-+-+ | | |
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|Run FF | ^ | +----+E' |
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| | | +-------->|E |
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| | +--------------+F' |
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| +--------------->|F |
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| | |
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| +---+ |cF41 |
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| +---+ +---+ | | | |
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+-------+ +->| | | Q+-->| +-->|CP1 +---> ALU,
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| | | & +-->|T | | | | | Register Kontrolle,
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| +-+ +--->| | | | | +-->|CP2 Kombinatorisches Schaltnetz +---> Speicher Kontrolle,
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| | | | +---+ |---| | | | | ...
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| -+ +- | | Q+-->| +-->|CP3 | ...
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| | | | | | | | Flags:
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+-------+ | | | +-->|CP4 |<--- Signum, Zero, Overflow, Carry, ...
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Oscillator |---| | | | |
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| Q+-->| +-->|CP5 |
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| | | | | |
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8-Phasen | | | +-->|CP6 |
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Taktgeber +---+ | | | |
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3 Bit | +-->|CP7 |
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Zähler | | | |
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| +-->|CP8 |
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| | | |
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+---+ +-----------------------------------------------------------------+
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3 zu 8 Decoder
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@enduml
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```
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## Kombinatorik für 2 Zyklusbefehle am Beispiel der Arithmetischen Operationen
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![kombinatorik1](./images/11_Modell_CPU/kombinatorik1.svg)
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![kombinatorik2](./images/11_Modell_CPU/kombinatorik2.svg)
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![kombinatorik3](./images/11_Modell_CPU/kombinatorik3.svg)
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![kombinatorik4](./images/11_Modell_CPU/kombinatorik4.svg)
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## Kontroll Schaltung als Statemachine mit Kombinatorischer Logik
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```text @plantUML.png
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@startuml
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ditaa
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+----------------------------------+
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|c42C +------->
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| |
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| +-------> Kontroll
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| | Signale
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| Kombinatorische Logik +------->
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| |
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| +------->
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| |
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| +------+
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+-+-+-+-+---+----------+-----------+ |
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^ ^ ^ ^ ^ ^Aktueller |
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| | | | | | Zustand |
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| | | | | +----+-----------+ |
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| | | | | |Zustandsspeicher| |
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| | | | | |cC42 | |
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| | | | | | +--+ +--+ | |
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| | | | | | |FF| |FF| ... | |
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| | | | | | +--+ +--+ | |
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| | | | | +------------+---+ |
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| | | | | ^ ^ |
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Opcode | | | |
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Alu States | | |
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| +----------+
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| Neuer Zustand
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|
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Clock
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@enduml
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```
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```text @plantUML.png
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@startuml
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state "Fetch1\n(memory read)" as Fetch1 : MBR ← M[MAR]
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state "Fetch2\n(wait for memory read)" as Fetch2 : (wait)
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state "Fetch3\n(increment program counter)" as Fetch3 : PC ← PC+1
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state "Fetch4\n(instruction load)" as Fetch4 : IR ← MBR
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state "Fetch5,6\n(instruction decoding...)" as Fetch56 : (wait)
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state decodefork <<fork>>
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state "Hlt\n(Set Halt signal)" as Hlt : RF ← H
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state "Wait\n(wait unitl CP8)" as Wait : (wait)
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state "Jmp\n(Set Programcounter to Operant)" as Jmp : PC ← IR_11-0
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state jmafork <<fork>> : Evaluate A_15
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state "Csa\n(load switches state to a)" as Csa : A ← SWR
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state "Jsr1\n(Set Programcounter to Operant)" as Jsr1 : A ← PC_11-0
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state "Jsr2\n(special Fetch0, load Operant to MBR and program counter)" as Jsr2 : MBR ← IR_11-0\nPC ← IR_11-0
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state "Fetch0\n(prepare instruction load)" as Fetch0 : MAR ← PC
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state "Other Operations ..." as OTHER : ...
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state "Rest\n(reset program counter)" as Reset : PC ← 0x0000
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[*] --> Reset
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Reset --> Fetch0
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Fetch0 --> Fetch1 : CP1
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Fetch1 --> Fetch2 : CP2
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Fetch2 --> Fetch3 : CP3
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Fetch3 --> Fetch4 : CP4
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Fetch4 --> Fetch56 : CP5
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Fetch56 --> decodefork : CP7
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decodefork --> Hlt : op == HLT
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decodefork --> Wait : op == NOP
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decodefork --> Jmp : op == JMP
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decodefork --> jmafork : op == JMA
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jmafork --> Jmp : A_15 == 1
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jmafork --> Wait : A_15 == 0
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decodefork --> Csa : op == CSA
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decodefork --> Jsr1 : op == JSR
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decodefork --> OTHER : op == RAL,NOT,LDA,STA,ADD,XOR,AND,IOR
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Hlt --> Fetch0 : CP8
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Jmp --> Fetch0 : CP8
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Wait --> Fetch0 : CP8
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Csa --> Fetch0 : CP8
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Jsr1 --> Jsr2 : CP8
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Jsr2 --> Fetch1 : CP1
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OTHER --> Fetch0 : CP8 (Execute Phase)
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@enduml
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```
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## Kontroll Schaltung als Statemachine mit Mikroprogrammspeicher
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```text @plantUML.png
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@startuml
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ditaa
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+----------------------------------+
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|c8C2 +------->
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| |
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| +-------> Kontroll
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| | Signale
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| Mikroprogramm Speicher +------->
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| |
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| +------->
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| |
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| +-------+
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+-+--------------------------------+ |
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^ ^Aktuelle Microcode |
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| |Instruction Adresse|
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| +-----------------+-----------+ |
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| |Adressspeicher | |
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Alu States| | | |
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| | +--+ +--+ +--+ | |
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| |FF| |FF| |FF| ... | |
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| +--+ +--+ +--+ cC42| |
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+-----------------------------+ |
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^ ^Folgeadresse |
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| | |
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| +----------+----------+ |
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| | Adress Generierung | |
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Clock| |cFF0 | |
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| ++-+-+-+------------+-+ |
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^ ^ ^ ^ ^ |
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| | | | | |
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| | | | | |
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Opcodes +-----------+
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Folgezustands
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Kontrolle
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@enduml
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```
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Die Folgeadresse ergibt sich aus dem Folgezustand und bem Operation Decode aus dem Opcode.
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Die Wörter im Mikroprogram Speicher enthalten Informationen zu den Kontroll Signalen und der Folgezustandkontrolle.

‎images/11_Modell_CPU/kombinatorik.odg‎

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