clk: adding items for some hdmi resolutions

1.
After changed pll source to npll for dclk_vop0,
some VGA screen appear noise/joggling when using
HDMI2VGA dongle.

To solve this issue we need to tune clk parameters
to make sure hdmi get less signal jitter as possible.

Fout = ((Fin /NR) * NF )/ NO
_#define RK3066_PLL_RATE(_rate, _nr, _nf, _no)

where Fout is targe clk, Fin is a clock oscillator 24M,
NR is reference divider, NF is multiplication factor,
NO is post vco divider, to get less jitter we need to
set maximum NO as possible.

2.
PLL supports Output frequency range within 27.5MHz – 2200MHz,
we need limit support freq. in vop driver.

Change-Id: Ifc6cfa2bd8a6ae88c2c9919e53e67d1b468bfacf

Author: ck_zhang

drivers/clk/rockchip/clk-rk3288.c

@@ -96,11 +96,30 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
 	RK3066_PLL_RATE( 300000000, 1, 50, 4),
 	RK3066_PLL_RATE( 297000000, 2, 198, 8),
+	RK3066_PLL_RATE_NB( 241500000, 2, 161, 8, 1),//2560*1440@60Hz
 	RK3066_PLL_RATE( 252000000, 1, 84, 8),
 	RK3066_PLL_RATE( 216000000, 1, 72, 8),
-	RK3066_PLL_RATE( 148500000, 2, 99, 8),
+	RK3066_PLL_RATE( 148500000, 2, 297, 24),//1920*1080@75
+	RK3066_PLL_RATE( 135000000, 2, 315, 28),//1280*1024@75
 	RK3066_PLL_RATE( 126000000, 1, 84, 16),
+	RK3066_PLL_RATE( 119000000, 3, 357, 24),//1680*1050@60
+	RK3066_PLL_RATE( 108000000, 1, 135, 30),//1280*1024@60
+	RK3066_PLL_RATE( 88750000, 4, 355, 24),//1440*900@60
+	RK3066_PLL_RATE( 71000000, 4, 355, 30),//1280*800@@60
+	RK3066_PLL_RATE( 74250000, 8, 297, 12),//1280*700@60
+	RK3066_PLL_RATE( 78800000, 2, 197, 30),//1280*720@60
+	RK3066_PLL_RATE( 75000000, 4, 375, 30),//1024*768@70
+	RK3066_PLL_RATE( 65000000, 3, 260, 32),//1024*768@@60
+	RK3066_PLL_RATE( 136750000, 4, 547, 24),//1440*900@75
+	RK3066_PLL_RATE( 106500000, 4, 497, 28),//1280*800@75, 1440*900@60
+	RK3066_PLL_RATE( 67500000, 8, 315, 14),//640*480@75
+	RK3066_PLL_RATE( 54000000, 4, 162, 18),//640*480@60
+	RK3066_PLL_RATE( 49500000, 1, 33, 16),//800*600@75
 	RK3066_PLL_RATE(  48000000, 1, 64, 32),
+	RK3066_PLL_RATE( 40000000, 1, 40, 24),//800*600@60
+	RK3066_PLL_RATE( 35500000, 3, 71, 16),//?
+	RK3066_PLL_RATE( 31500000, 3, 73, 16),//640*480@75
+	RK3066_PLL_RATE( 28320000, 5, 177, 30), //720*400@70
 	{ /* sentinel */ },
 };
 

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

@@ -1494,7 +1494,7 @@ vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 	const struct vop_data *vop_data = vop->data;
 	int clock;
 
-	if (mode->clock >= 594000)
+	if (mode->clock >= 594000 || mode->clock <= 27500)
 		return MODE_CLOCK_RANGE;
 
 	if (mode->hdisplay > vop_data->max_disably_output.width)