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Merge branch 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Radeon and amdgpu fixes for 4.4: - DPM fixes for r7xx devices - VCE fixes for Stoney - GPUVM fixes - Scheduler fixes * 'drm-fixes-4.4' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: make some dpm errors debug only drm/radeon: make rv770_set_sw_state failures non-fatal drm/amdgpu: move dependency handling out of atomic section v2 drm/amdgpu: optimize scheduler fence handling drm/amdgpu: remove vm->mutex drm/amdgpu: add mutex for ba_va->valids/invalids drm/amdgpu: adapt vce session create interface changes drm/amdgpu: vce use multiple cache surface starting from stoney drm/amdgpu: reset vce trap interrupt flag
2 parents 78c4a49 + 9c565e3 commit 2f13716

11 files changed

Lines changed: 145 additions & 76 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,7 @@ struct amdgpu_bo_va_mapping {
496496

497497
/* bo virtual addresses in a specific vm */
498498
struct amdgpu_bo_va {
499+
struct mutex mutex;
499500
/* protected by bo being reserved */
500501
struct list_head bo_list;
501502
struct fence *last_pt_update;
@@ -928,8 +929,6 @@ struct amdgpu_vm_id {
928929
};
929930

930931
struct amdgpu_vm {
931-
struct mutex mutex;
932-
933932
struct rb_root va;
934933

935934
/* protecting invalidated */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -784,8 +784,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
784784
{
785785
struct amdgpu_device *adev = dev->dev_private;
786786
union drm_amdgpu_cs *cs = data;
787-
struct amdgpu_fpriv *fpriv = filp->driver_priv;
788-
struct amdgpu_vm *vm = &fpriv->vm;
789787
struct amdgpu_cs_parser parser = {};
790788
bool reserved_buffers = false;
791789
int i, r;
@@ -803,7 +801,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
803801
r = amdgpu_cs_handle_lockup(adev, r);
804802
return r;
805803
}
806-
mutex_lock(&vm->mutex);
807804
r = amdgpu_cs_parser_relocs(&parser);
808805
if (r == -ENOMEM)
809806
DRM_ERROR("Not enough memory for command submission!\n");
@@ -888,7 +885,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
888885

889886
out:
890887
amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
891-
mutex_unlock(&vm->mutex);
892888
r = amdgpu_cs_handle_lockup(adev, r);
893889
return r;
894890
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -115,12 +115,9 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
115115
struct amdgpu_vm *vm = &fpriv->vm;
116116
struct amdgpu_bo_va *bo_va;
117117
int r;
118-
mutex_lock(&vm->mutex);
119118
r = amdgpu_bo_reserve(rbo, false);
120-
if (r) {
121-
mutex_unlock(&vm->mutex);
119+
if (r)
122120
return r;
123-
}
124121

125122
bo_va = amdgpu_vm_bo_find(vm, rbo);
126123
if (!bo_va) {
@@ -129,7 +126,6 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
129126
++bo_va->ref_count;
130127
}
131128
amdgpu_bo_unreserve(rbo);
132-
mutex_unlock(&vm->mutex);
133129
return 0;
134130
}
135131

@@ -142,10 +138,8 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
142138
struct amdgpu_vm *vm = &fpriv->vm;
143139
struct amdgpu_bo_va *bo_va;
144140
int r;
145-
mutex_lock(&vm->mutex);
146141
r = amdgpu_bo_reserve(rbo, true);
147142
if (r) {
148-
mutex_unlock(&vm->mutex);
149143
dev_err(adev->dev, "leaking bo va because "
150144
"we fail to reserve bo (%d)\n", r);
151145
return;
@@ -157,7 +151,6 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
157151
}
158152
}
159153
amdgpu_bo_unreserve(rbo);
160-
mutex_unlock(&vm->mutex);
161154
}
162155

163156
static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
@@ -553,7 +546,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
553546
gobj = drm_gem_object_lookup(dev, filp, args->handle);
554547
if (gobj == NULL)
555548
return -ENOENT;
556-
mutex_lock(&fpriv->vm.mutex);
557549
rbo = gem_to_amdgpu_bo(gobj);
558550
INIT_LIST_HEAD(&list);
559551
INIT_LIST_HEAD(&duplicates);
@@ -568,7 +560,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
568560
}
569561
r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
570562
if (r) {
571-
mutex_unlock(&fpriv->vm.mutex);
572563
drm_gem_object_unreference_unlocked(gobj);
573564
return r;
574565
}
@@ -577,7 +568,6 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
577568
if (!bo_va) {
578569
ttm_eu_backoff_reservation(&ticket, &list);
579570
drm_gem_object_unreference_unlocked(gobj);
580-
mutex_unlock(&fpriv->vm.mutex);
581571
return -ENOENT;
582572
}
583573

@@ -602,7 +592,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
602592
ttm_eu_backoff_reservation(&ticket, &list);
603593
if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
604594
amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
605-
mutex_unlock(&fpriv->vm.mutex);
595+
606596
drm_gem_object_unreference_unlocked(gobj);
607597
return r;
608598
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -392,7 +392,10 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
392392
ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
393393
ib->ptr[ib->length_dw++] = handle;
394394

395-
ib->ptr[ib->length_dw++] = 0x00000030; /* len */
395+
if ((ring->adev->vce.fw_version >> 24) >= 52)
396+
ib->ptr[ib->length_dw++] = 0x00000040; /* len */
397+
else
398+
ib->ptr[ib->length_dw++] = 0x00000030; /* len */
396399
ib->ptr[ib->length_dw++] = 0x01000001; /* create cmd */
397400
ib->ptr[ib->length_dw++] = 0x00000000;
398401
ib->ptr[ib->length_dw++] = 0x00000042;
@@ -404,6 +407,12 @@ int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
404407
ib->ptr[ib->length_dw++] = 0x00000100;
405408
ib->ptr[ib->length_dw++] = 0x0000000c;
406409
ib->ptr[ib->length_dw++] = 0x00000000;
410+
if ((ring->adev->vce.fw_version >> 24) >= 52) {
411+
ib->ptr[ib->length_dw++] = 0x00000000;
412+
ib->ptr[ib->length_dw++] = 0x00000000;
413+
ib->ptr[ib->length_dw++] = 0x00000000;
414+
ib->ptr[ib->length_dw++] = 0x00000000;
415+
}
407416

408417
ib->ptr[ib->length_dw++] = 0x00000014; /* len */
409418
ib->ptr[ib->length_dw++] = 0x05000005; /* feedback buffer */

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -922,8 +922,9 @@ int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
922922
bo_va = list_first_entry(&vm->invalidated,
923923
struct amdgpu_bo_va, vm_status);
924924
spin_unlock(&vm->status_lock);
925-
925+
mutex_lock(&bo_va->mutex);
926926
r = amdgpu_vm_bo_update(adev, bo_va, NULL);
927+
mutex_unlock(&bo_va->mutex);
927928
if (r)
928929
return r;
929930

@@ -967,7 +968,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
967968
INIT_LIST_HEAD(&bo_va->valids);
968969
INIT_LIST_HEAD(&bo_va->invalids);
969970
INIT_LIST_HEAD(&bo_va->vm_status);
970-
971+
mutex_init(&bo_va->mutex);
971972
list_add_tail(&bo_va->bo_list, &bo->va);
972973

973974
return bo_va;
@@ -1045,7 +1046,9 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
10451046
mapping->offset = offset;
10461047
mapping->flags = flags;
10471048

1049+
mutex_lock(&bo_va->mutex);
10481050
list_add(&mapping->list, &bo_va->invalids);
1051+
mutex_unlock(&bo_va->mutex);
10491052
spin_lock(&vm->it_lock);
10501053
interval_tree_insert(&mapping->it, &vm->va);
10511054
spin_unlock(&vm->it_lock);
@@ -1121,7 +1124,7 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
11211124
bool valid = true;
11221125

11231126
saddr /= AMDGPU_GPU_PAGE_SIZE;
1124-
1127+
mutex_lock(&bo_va->mutex);
11251128
list_for_each_entry(mapping, &bo_va->valids, list) {
11261129
if (mapping->it.start == saddr)
11271130
break;
@@ -1135,10 +1138,12 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
11351138
break;
11361139
}
11371140

1138-
if (&mapping->list == &bo_va->invalids)
1141+
if (&mapping->list == &bo_va->invalids) {
1142+
mutex_unlock(&bo_va->mutex);
11391143
return -ENOENT;
1144+
}
11401145
}
1141-
1146+
mutex_unlock(&bo_va->mutex);
11421147
list_del(&mapping->list);
11431148
spin_lock(&vm->it_lock);
11441149
interval_tree_remove(&mapping->it, &vm->va);
@@ -1190,8 +1195,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
11901195
spin_unlock(&vm->it_lock);
11911196
kfree(mapping);
11921197
}
1193-
11941198
fence_put(bo_va->last_pt_update);
1199+
mutex_destroy(&bo_va->mutex);
11951200
kfree(bo_va);
11961201
}
11971202

@@ -1236,7 +1241,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
12361241
vm->ids[i].id = 0;
12371242
vm->ids[i].flushed_updates = NULL;
12381243
}
1239-
mutex_init(&vm->mutex);
12401244
vm->va = RB_ROOT;
12411245
spin_lock_init(&vm->status_lock);
12421246
INIT_LIST_HEAD(&vm->invalidated);
@@ -1320,7 +1324,6 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
13201324
fence_put(vm->ids[i].flushed_updates);
13211325
}
13221326

1323-
mutex_destroy(&vm->mutex);
13241327
}
13251328

13261329
/**

‎drivers/gpu/drm/amd/amdgpu/vce_v3_0.c‎

Lines changed: 19 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,9 @@
4040

4141
#define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
4242
#define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
43+
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
44+
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
45+
#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
4346

4447
#define VCE_V3_0_FW_SIZE (384 * 1024)
4548
#define VCE_V3_0_STACK_SIZE (64 * 1024)
@@ -130,9 +133,11 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
130133

131134
/* set BUSY flag */
132135
WREG32_P(mmVCE_STATUS, 1, ~1);
133-
134-
WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
135-
~VCE_VCPU_CNTL__CLK_EN_MASK);
136+
if (adev->asic_type >= CHIP_STONEY)
137+
WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
138+
else
139+
WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
140+
~VCE_VCPU_CNTL__CLK_EN_MASK);
136141

137142
WREG32_P(mmVCE_SOFT_RESET,
138143
VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
@@ -391,8 +396,12 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)
391396
WREG32(mmVCE_LMI_SWAP_CNTL, 0);
392397
WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
393398
WREG32(mmVCE_LMI_VM_CTRL, 0);
394-
395-
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
399+
if (adev->asic_type >= CHIP_STONEY) {
400+
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
401+
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
402+
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
403+
} else
404+
WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
396405
offset = AMDGPU_VCE_FIRMWARE_OFFSET;
397406
size = VCE_V3_0_FW_SIZE;
398407
WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
@@ -576,6 +585,11 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
576585
struct amdgpu_iv_entry *entry)
577586
{
578587
DRM_DEBUG("IH: VCE\n");
588+
589+
WREG32_P(mmVCE_SYS_INT_STATUS,
590+
VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK,
591+
~VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK);
592+
579593
switch (entry->src_data) {
580594
case 0:
581595
amdgpu_fence_process(&adev->vce.ring[0]);

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