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xubilvrkhuangtao
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drm/rockchip: dw-mipi-dsi: organize dw_mipi_dsi_encoder_enable function
Change-Id: I9d3f43f9d320cc33026bce2ce173a0baf3008ce0 Signed-off-by: xubilv <xbl@rock-chips.com>
1 parent 3c5e401 commit 39d1c0c

1 file changed

Lines changed: 46 additions & 44 deletions

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drivers/gpu/drm/rockchip/dw-mipi-dsi.c

Lines changed: 46 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -352,19 +352,6 @@ static int max_mbps_to_testdin(unsigned int max_mbps)
352352
return -EINVAL;
353353
}
354354

355-
/*
356-
* The controller should generate 2 frames before
357-
* preparing the peripheral.
358-
*/
359-
static void dw_mipi_dsi_wait_for_two_frames(struct dw_mipi_dsi *dsi)
360-
{
361-
int refresh, two_frames;
362-
363-
refresh = drm_mode_vrefresh(&dsi->mode);
364-
two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
365-
msleep(two_frames);
366-
}
367-
368355
static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
369356
{
370357
return container_of(host, struct dw_mipi_dsi, dsi_host);
@@ -905,19 +892,30 @@ static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
905892
return true;
906893
}
907894

908-
static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
895+
static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
909896
{
910-
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
911897
const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
912-
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
913-
int ret;
914-
u32 val;
898+
int val = 0;
915899

900+
if (vop_id)
901+
val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
902+
else
903+
val = pdata->dsi0_en_bit << 16;
904+
905+
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
906+
907+
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
908+
}
909+
910+
static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
911+
{
916912
if (clk_prepare_enable(dsi->pclk)) {
917913
dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
918914
return;
919915
}
920916

917+
pm_runtime_get_sync(dsi->dev);
918+
921919
if (dsi->rst) {
922920
/* MIPI DSI APB software reset request. */
923921
reset_control_assert(dsi->rst);
@@ -926,22 +924,21 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
926924
udelay(10);
927925
}
928926

929-
pm_runtime_get_sync(dsi->dev);
930-
931-
phy_power_on(dsi->phy);
932-
933927
if (dsi->phy) {
928+
phy_power_on(dsi->phy);
929+
934930
/*
935931
* If using the third party PHY, we get the lane
936932
* rate information from PHY.
937933
*/
938934
dsi->lane_mbps = phy_get_bus_width(dsi->phy);
939935
} else {
940-
ret = dw_mipi_dsi_get_lane_bps(dsi);
941-
if (ret < 0)
942-
return;
936+
dw_mipi_dsi_get_lane_bps(dsi);
943937
}
938+
}
944939

940+
static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
941+
{
945942
dw_mipi_dsi_init(dsi);
946943
dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
947944
dw_mipi_dsi_packet_handler_config(dsi);
@@ -953,33 +950,38 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
953950
dw_mipi_dsi_dphy_timing_config(dsi);
954951
dw_mipi_dsi_dphy_interface_config(dsi);
955952
dw_mipi_dsi_clear_err(dsi);
956-
if (drm_panel_prepare(dsi->panel))
957-
dev_err(dsi->dev, "failed to prepare panel\n");
953+
}
958954

959-
if (pdata->grf_dsi0_mode_reg)
960-
regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
961-
pdata->grf_dsi0_mode);
955+
static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
956+
{
957+
rockchip_dsi_pre_init(dsi);
958+
rockchip_dsi_host_init(dsi);
959+
dw_mipi_dsi_phy_init(dsi);
960+
}
962961

963-
if (!dsi->phy)
964-
dw_mipi_dsi_phy_init(dsi);
962+
static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
963+
{
964+
dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
965+
clk_disable_unprepare(dsi->pclk);
966+
}
965967

966-
dw_mipi_dsi_wait_for_two_frames(dsi);
968+
static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
969+
{
970+
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
971+
int vop_id;
967972

968-
dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
969-
drm_panel_enable(dsi->panel);
973+
vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
970974

971-
clk_disable_unprepare(dsi->pclk);
975+
rockchip_dsi_grf_config(dsi, vop_id);
976+
rockchip_dsi_init(dsi);
972977

973-
if (!pdata->has_vop_sel)
974-
return;
978+
if (dsi->panel)
979+
drm_panel_prepare(dsi->panel);
975980

976-
if (mux)
977-
val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
978-
else
979-
val = pdata->dsi0_en_bit << 16;
981+
rockchip_dsi_enable(dsi);
980982

981-
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
982-
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
983+
if (dsi->panel)
984+
drm_panel_enable(dsi->panel);
983985
}
984986

985987
static int

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