1111
1212#include <linux/pci.h>
1313#include <linux/acpi.h>
14+ #include <linux/delay.h>
15+ #include <linux/dmi.h>
1416#include <linux/pci_ids.h>
17+ #include <linux/bcma/bcma.h>
18+ #include <linux/bcma/bcma_regs.h>
1519#include <drm/i915_drm.h>
1620#include <asm/pci-direct.h>
1721#include <asm/dma.h>
2125#include <asm/iommu.h>
2226#include <asm/gart.h>
2327#include <asm/irq_remapping.h>
28+ #include <asm/early_ioremap.h>
29+
30+ #define dev_err (msg ) pr_err("pci 0000:%02x:%02x.%d: %s", bus, slot, func, msg)
2431
2532static void __init fix_hypertransport_config (int num , int slot , int func )
2633{
@@ -75,6 +82,13 @@ static void __init nvidia_bugs(int num, int slot, int func)
7582{
7683#ifdef CONFIG_ACPI
7784#ifdef CONFIG_X86_IO_APIC
85+ /*
86+ * Only applies to Nvidia root ports (bus 0) and not to
87+ * Nvidia graphics cards with PCI ports on secondary buses.
88+ */
89+ if (num )
90+ return ;
91+
7892 /*
7993 * All timer overrides on Nvidia are
8094 * wrong unless HPET is enabled.
@@ -589,6 +603,61 @@ static void __init force_disable_hpet(int num, int slot, int func)
589603#endif
590604}
591605
606+ #define BCM4331_MMIO_SIZE 16384
607+ #define BCM4331_PM_CAP 0x40
608+ #define bcma_aread32 (reg ) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
609+ #define bcma_awrite32 (reg , val ) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
610+
611+ static void __init apple_airport_reset (int bus , int slot , int func )
612+ {
613+ void __iomem * mmio ;
614+ u16 pmcsr ;
615+ u64 addr ;
616+ int i ;
617+
618+ if (!dmi_match (DMI_SYS_VENDOR , "Apple Inc." ))
619+ return ;
620+
621+ /* Card may have been put into PCI_D3hot by grub quirk */
622+ pmcsr = read_pci_config_16 (bus , slot , func , BCM4331_PM_CAP + PCI_PM_CTRL );
623+
624+ if ((pmcsr & PCI_PM_CTRL_STATE_MASK ) != PCI_D0 ) {
625+ pmcsr &= ~PCI_PM_CTRL_STATE_MASK ;
626+ write_pci_config_16 (bus , slot , func , BCM4331_PM_CAP + PCI_PM_CTRL , pmcsr );
627+ mdelay (10 );
628+
629+ pmcsr = read_pci_config_16 (bus , slot , func , BCM4331_PM_CAP + PCI_PM_CTRL );
630+ if ((pmcsr & PCI_PM_CTRL_STATE_MASK ) != PCI_D0 ) {
631+ dev_err ("Cannot power up Apple AirPort card\n" );
632+ return ;
633+ }
634+ }
635+
636+ addr = read_pci_config (bus , slot , func , PCI_BASE_ADDRESS_0 );
637+ addr |= (u64 )read_pci_config (bus , slot , func , PCI_BASE_ADDRESS_1 ) << 32 ;
638+ addr &= PCI_BASE_ADDRESS_MEM_MASK ;
639+
640+ mmio = early_ioremap (addr , BCM4331_MMIO_SIZE );
641+ if (!mmio ) {
642+ dev_err ("Cannot iomap Apple AirPort card\n" );
643+ return ;
644+ }
645+
646+ pr_info ("Resetting Apple AirPort card (left enabled by EFI)\n" );
647+
648+ for (i = 0 ; bcma_aread32 (BCMA_RESET_ST ) && i < 30 ; i ++ )
649+ udelay (10 );
650+
651+ bcma_awrite32 (BCMA_RESET_CTL , BCMA_RESET_CTL_RESET );
652+ bcma_aread32 (BCMA_RESET_CTL );
653+ udelay (1 );
654+
655+ bcma_awrite32 (BCMA_RESET_CTL , 0 );
656+ bcma_aread32 (BCMA_RESET_CTL );
657+ udelay (10 );
658+
659+ early_iounmap (mmio , BCM4331_MMIO_SIZE );
660+ }
592661
593662#define QFLAG_APPLY_ONCE 0x1
594663#define QFLAG_APPLIED 0x2
@@ -602,12 +671,6 @@ struct chipset {
602671 void (* f )(int num , int slot , int func );
603672};
604673
605- /*
606- * Only works for devices on the root bus. If you add any devices
607- * not on bus 0 readd another loop level in early_quirks(). But
608- * be careful because at least the Nvidia quirk here relies on
609- * only matching on bus 0.
610- */
611674static struct chipset early_qrk [] __initdata = {
612675 { PCI_VENDOR_ID_NVIDIA , PCI_ANY_ID ,
613676 PCI_CLASS_BRIDGE_PCI , PCI_ANY_ID , QFLAG_APPLY_ONCE , nvidia_bugs },
@@ -637,9 +700,13 @@ static struct chipset early_qrk[] __initdata = {
637700 */
638701 { PCI_VENDOR_ID_INTEL , 0x0f00 ,
639702 PCI_CLASS_BRIDGE_HOST , PCI_ANY_ID , 0 , force_disable_hpet },
703+ { PCI_VENDOR_ID_BROADCOM , 0x4331 ,
704+ PCI_CLASS_NETWORK_OTHER , PCI_ANY_ID , 0 , apple_airport_reset },
640705 {}
641706};
642707
708+ static void __init early_pci_scan_bus (int bus );
709+
643710/**
644711 * check_dev_quirk - apply early quirks to a given PCI device
645712 * @num: bus number
@@ -648,7 +715,7 @@ static struct chipset early_qrk[] __initdata = {
648715 *
649716 * Check the vendor & device ID against the early quirks table.
650717 *
651- * If the device is single function, let early_quirks () know so we don't
718+ * If the device is single function, let early_pci_scan_bus () know so we don't
652719 * poke at this device again.
653720 */
654721static int __init check_dev_quirk (int num , int slot , int func )
@@ -657,6 +724,7 @@ static int __init check_dev_quirk(int num, int slot, int func)
657724 u16 vendor ;
658725 u16 device ;
659726 u8 type ;
727+ u8 sec ;
660728 int i ;
661729
662730 class = read_pci_config_16 (num , slot , func , PCI_CLASS_DEVICE );
@@ -684,25 +752,36 @@ static int __init check_dev_quirk(int num, int slot, int func)
684752
685753 type = read_pci_config_byte (num , slot , func ,
686754 PCI_HEADER_TYPE );
755+
756+ if ((type & 0x7f ) == PCI_HEADER_TYPE_BRIDGE ) {
757+ sec = read_pci_config_byte (num , slot , func , PCI_SECONDARY_BUS );
758+ if (sec > num )
759+ early_pci_scan_bus (sec );
760+ }
761+
687762 if (!(type & 0x80 ))
688763 return -1 ;
689764
690765 return 0 ;
691766}
692767
693- void __init early_quirks ( void )
768+ static void __init early_pci_scan_bus ( int bus )
694769{
695770 int slot , func ;
696771
697- if (!early_pci_allowed ())
698- return ;
699-
700772 /* Poor man's PCI discovery */
701- /* Only scan the root bus */
702773 for (slot = 0 ; slot < 32 ; slot ++ )
703774 for (func = 0 ; func < 8 ; func ++ ) {
704775 /* Only probe function 0 on single fn devices */
705- if (check_dev_quirk (0 , slot , func ))
776+ if (check_dev_quirk (bus , slot , func ))
706777 break ;
707778 }
708779}
780+
781+ void __init early_quirks (void )
782+ {
783+ if (!early_pci_allowed ())
784+ return ;
785+
786+ early_pci_scan_bus (0 );
787+ }
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