arm: dts: rockchip: Add clock assign for rk3126 and rk3128 cru

Add "assigned-clocks" for rk3126 and rk3128 cru nodes, to intalize
clock rate for plls, bus and peripher.

Change-Id: Ie91c8b194feff5db91af6e9930d5f475175242f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Author: finley1226

arch/arm/boot/dts/rk3126.dtsi

@@ -42,12 +42,8 @@
 
 / {
 	compatible = "rockchip,rk3126";
+};
 
-	cru: clock-controller@20000000 {
-		compatible = "rockchip,rk3126-cru";
-		reg = <0x20000000 0x1000>;
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
+&cru {
+	compatible = "rockchip,rk3126-cru";
 };

arch/arm/boot/dts/rk3128.dtsi

@@ -47,14 +47,6 @@
 		compatible = "syscon";
 		reg = <0x1012f080 0x20>;
 	};
-
-	cru: clock-controller@20000000 {
-		compatible = "rockchip,rk3128-cru";
-		reg = <0x20000000 0x1000>;
-		rockchip,grf = <&grf>;
-		#clock-cells = <1>;
-		#reset-cells = <1>;
-	};
 };
 
 &pd_vio {

arch/arm/boot/dts/rk312x.dtsi

@@ -743,6 +743,22 @@
 		status = "disabled";
 	};
 
+	cru: clock-controller@20000000 {
+		compatible = "rockchip,rk3128-cru";
+		reg = <0x20000000 0x1000>;
+		rockchip,grf = <&grf>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+				  <&cru HCLK_PERI>, <&cru PCLK_PERI>;
+		assigned-clock-rates = <594000000>, <400000000>,
+				       <300000000>, <150000000>,
+				       <75000000>, <300000000>,
+				       <150000000>, <75000000>;
+	};
+
 	grf: syscon@20008000 {
 		compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
 		reg = <0x20008000 0x1000>;