@@ -38,17 +38,21 @@ extern struct rga2_mmu_buf_t rga2_mmu_buf;
3838#define V7_VATOPA_GET_NS (X ) ((X>>9) & 1)
3939#define V7_VATOPA_GET_SS (X ) ((X>>1) & 1)
4040
41- static void rga_dma_flush_range (void * pstart , void * pend )
41+ void rga2_dma_flush_range (void * pstart , void * pend )
4242{
4343#ifdef CONFIG_ARM
4444 dmac_flush_range (pstart , pend );
4545 outer_flush_range (virt_to_phys (pstart ), virt_to_phys (pend ));
4646#elif defined(CONFIG_ARM64 )
47+ #if LINUX_VERSION_CODE >= KERNEL_VERSION (4 , 19 , 0 )
48+ __dma_flush_area (pstart , pend - pstart );
49+ #else
4750 __dma_flush_range (pstart , pend );
4851#endif
52+ #endif
4953}
5054
51- static void rga_dma_flush_page (struct page * page )
55+ static void rga2_dma_flush_page (struct page * page )
5256{
5357 phys_addr_t paddr ;
5458 void * virt ;
@@ -73,8 +77,12 @@ static void rga_dma_flush_page(struct page *page)
7377 outer_flush_range (paddr , paddr + PAGE_SIZE );
7478#elif defined(CONFIG_ARM64 )
7579 virt = page_address (page );
80+ #if LINUX_VERSION_CODE >= KERNEL_VERSION (4 , 19 , 0 )
81+ __dma_flush_area (virt , PAGE_SIZE );
82+ #else
7683 __dma_flush_range (virt , virt + PAGE_SIZE );
7784#endif
85+ #endif
7886}
7987
8088#if 0
@@ -436,14 +444,14 @@ static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
436444#else
437445 result = get_user_pages_remote (current , current -> mm ,
438446 Memory << PAGE_SHIFT ,
439- pageCount , writeFlag , 0 , pages , NULL );
447+ pageCount , writeFlag , pages , NULL , NULL );
440448#endif
441449 if (result > 0 && result >= pageCount ) {
442450 /* Fill the page table. */
443451 for (i = 0 ; i < pageCount ; i ++ ) {
444452 /* Get the physical address from page struct. */
445453 pageTable [i ] = page_to_phys (pages [i ]);
446- rga_dma_flush_page (pages [i ]);
454+ rga2_dma_flush_page (pages [i ]);
447455 }
448456 for (i = 0 ; i < result ; i ++ )
449457 put_page (pages [i ]);
@@ -491,7 +499,7 @@ static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
491499 Address = ((pfn << PAGE_SHIFT ) | (((unsigned long )((Memory + i )
492500 << PAGE_SHIFT )) & ~PAGE_MASK ));
493501 pageTable [i ] = (uint32_t )Address ;
494- rga_dma_flush_page (pfn_to_page (pfn ));
502+ rga2_dma_flush_page (pfn_to_page (pfn ));
495503 pte_unmap_unlock (pte , ptl );
496504 }
497505 up_read (& current -> mm -> mmap_sem );
@@ -702,7 +710,7 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
702710 }
703711 }
704712 /* flush data to DDR */
705- rga_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
713+ rga2_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
706714 rga2_mmu_buf_get (& rga2_mmu_buf , AllSize );
707715 reg -> MMU_len = AllSize ;
708716 status = 0 ;
@@ -801,7 +809,7 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
801809 }
802810
803811 /* flush data to DDR */
804- rga_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
812+ rga2_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
805813 rga2_mmu_buf_get (& rga2_mmu_buf , AllSize );
806814 reg -> MMU_len = AllSize ;
807815
@@ -870,7 +878,7 @@ static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *
870878 }
871879
872880 /* flush data to DDR */
873- rga_dma_flush_range (MMU_Base , (MMU_Base + AllSize + 1 ));
881+ rga2_dma_flush_range (MMU_Base , (MMU_Base + AllSize + 1 ));
874882 rga2_mmu_buf_get (& rga2_mmu_buf , AllSize );
875883 reg -> MMU_len = AllSize ;
876884
@@ -931,7 +939,7 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
931939 }
932940
933941 /* flush data to DDR */
934- rga_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
942+ rga2_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
935943 rga2_mmu_buf_get (& rga2_mmu_buf , AllSize );
936944 reg -> MMU_len = AllSize ;
937945
@@ -1010,7 +1018,7 @@ static int rga2_mmu_info_update_patten_buff_mode(struct rga2_reg *reg, struct rg
10101018 reg -> MMU_base = MMU_Base ;
10111019
10121020 /* flush data to DDR */
1013- rga_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
1021+ rga2_dma_flush_range (MMU_Base , (MMU_Base + AllSize ));
10141022 return 0 ;
10151023
10161024 }
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