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yc-hou-0919jamess-huang
yc-hou-0919
authored and
jamess-huang
committed
Fix Waveshare 7" HDMI USB no function issue
Change-Id: I44ec721b5491cd2512ec323cb9939cd79da8851e Reviewed-on: https://tp-biosrd-v02/gerrit/83047 Reviewed-by: Jamess Huang(黃以民) <Jamess_Huang@asus.com> Tested-by: Jamess Huang(黃以民) <Jamess_Huang@asus.com>
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11 files changed

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-2979
lines changed

11 files changed

+807
-2979
lines changed

‎drivers/usb/dwc2/core.c‎

100755100644
Lines changed: 61 additions & 143 deletions
Original file line numberDiff line numberDiff line change
@@ -313,64 +313,63 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
313313
* Do core a soft reset of the core. Be careful with this because it
314314
* resets all the internal state machines of the core.
315315
*/
316-
int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
316+
int dwc2_core_reset(struct dwc2_hsotg *hsotg)
317317
{
318318
u32 greset;
319319
int count = 0;
320-
bool wait_for_host_mode = false;
320+
u32 gusbcfg;
321321

322322
dev_vdbg(hsotg->dev, "%s()\n", __func__);
323323

324-
/*
325-
* If the current mode is host, either due to the force mode
326-
* bit being set (which persists after core reset) or the
327-
* connector id pin, a core soft reset will temporarily reset
328-
* the mode to device. A delay from the IDDIG debounce filter
329-
* will occur before going back to host mode.
330-
*
331-
* Determine whether we will go back into host mode after a
332-
* reset and account for this delay after the reset.
333-
*/
334-
if (dwc2_iddig_filter_enabled(hsotg)) {
335-
u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
336-
u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
337-
338-
if (!(gotgctl & GOTGCTL_CONID_B) ||
339-
(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
340-
wait_for_host_mode = true;
341-
}
342-
}
343-
344-
/* Core Soft Reset */
345-
greset = dwc2_readl(hsotg->regs + GRSTCTL);
346-
greset |= GRSTCTL_CSFTRST;
347-
dwc2_writel(greset, hsotg->regs + GRSTCTL);
324+
/* Wait for AHB master IDLE state */
348325
do {
349-
udelay(1);
326+
usleep_range(20000, 40000);
350327
greset = dwc2_readl(hsotg->regs + GRSTCTL);
351328
if (++count > 50) {
352329
dev_warn(hsotg->dev,
353-
"%s() HANG! Soft Reset GRSTCTL=%0x\n",
330+
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
354331
__func__, greset);
355332
return -EBUSY;
356333
}
357-
} while (greset & GRSTCTL_CSFTRST);
334+
} while (!(greset & GRSTCTL_AHBIDLE));
358335

359-
/* Wait for AHB master IDLE state */
336+
/* Core Soft Reset */
360337
count = 0;
338+
greset |= GRSTCTL_CSFTRST;
339+
dwc2_writel(greset, hsotg->regs + GRSTCTL);
361340
do {
362-
udelay(1);
341+
usleep_range(20000, 40000);
363342
greset = dwc2_readl(hsotg->regs + GRSTCTL);
364343
if (++count > 50) {
365344
dev_warn(hsotg->dev,
366-
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
345+
"%s() HANG! Soft Reset GRSTCTL=%0x\n",
367346
__func__, greset);
368347
return -EBUSY;
369348
}
370-
} while (!(greset & GRSTCTL_AHBIDLE));
349+
} while (greset & GRSTCTL_CSFTRST);
371350

372-
if (wait_for_host_mode && !skip_wait)
373-
dwc2_wait_for_mode(hsotg, true);
351+
if (hsotg->dr_mode == USB_DR_MODE_HOST) {
352+
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
353+
gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
354+
gusbcfg |= GUSBCFG_FORCEHOSTMODE;
355+
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
356+
} else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
357+
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
358+
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
359+
gusbcfg |= GUSBCFG_FORCEDEVMODE;
360+
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
361+
} else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
362+
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
363+
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
364+
gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
365+
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
366+
}
367+
368+
/*
369+
* NOTE: This long sleep is _very_ important, otherwise the core will
370+
* not stay in host mode after a connector ID change!
371+
*/
372+
usleep_range(150000, 200000);
374373

375374
return 0;
376375
}
@@ -503,7 +502,7 @@ int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
503502
{
504503
int retval;
505504

506-
retval = dwc2_core_reset(hsotg, false);
505+
retval = dwc2_core_reset(hsotg);
507506
if (retval)
508507
return retval;
509508

@@ -838,29 +837,6 @@ void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
838837
hsotg->core_params->dma_desc_enable = val;
839838
}
840839

841-
void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
842-
{
843-
int valid = 1;
844-
845-
if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
846-
!hsotg->hw_params.dma_desc_enable))
847-
valid = 0;
848-
if (val < 0)
849-
valid = 0;
850-
851-
if (!valid) {
852-
if (val >= 0)
853-
dev_err(hsotg->dev,
854-
"%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
855-
val);
856-
val = (hsotg->core_params->dma_enable > 0 &&
857-
hsotg->hw_params.dma_desc_enable);
858-
}
859-
860-
hsotg->core_params->dma_desc_fs_enable = val;
861-
dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
862-
}
863-
864840
void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
865841
int val)
866842
{
@@ -1392,7 +1368,6 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
13921368
dwc2_set_param_otg_cap(hsotg, params->otg_cap);
13931369
dwc2_set_param_dma_enable(hsotg, params->dma_enable);
13941370
dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
1395-
dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
13961371
dwc2_set_param_host_support_fs_ls_low_power(hsotg,
13971372
params->host_support_fs_ls_low_power);
13981373
dwc2_set_param_enable_dynamic_fifo(hsotg,
@@ -1429,79 +1404,6 @@ void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
14291404
dwc2_set_param_hibernation(hsotg, params->hibernation);
14301405
}
14311406

1432-
/*
1433-
* Forces either host or device mode if the controller is not
1434-
* currently in that mode.
1435-
*
1436-
* Returns true if the mode was forced.
1437-
*/
1438-
static bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host)
1439-
{
1440-
if (host && dwc2_is_host_mode(hsotg))
1441-
return false;
1442-
else if (!host && dwc2_is_device_mode(hsotg))
1443-
return false;
1444-
1445-
return dwc2_force_mode(hsotg, host);
1446-
}
1447-
1448-
/*
1449-
* Gets host hardware parameters. Forces host mode if not currently in
1450-
* host mode. Should be called immediately after a core soft reset in
1451-
* order to get the reset values.
1452-
*/
1453-
static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
1454-
{
1455-
struct dwc2_hw_params *hw = &hsotg->hw_params;
1456-
u32 gnptxfsiz;
1457-
u32 hptxfsiz;
1458-
bool forced;
1459-
1460-
if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
1461-
return;
1462-
1463-
forced = dwc2_force_mode_if_needed(hsotg, true);
1464-
1465-
gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1466-
hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1467-
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1468-
dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1469-
1470-
if (forced)
1471-
dwc2_clear_force_mode(hsotg);
1472-
1473-
hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1474-
FIFOSIZE_DEPTH_SHIFT;
1475-
hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1476-
FIFOSIZE_DEPTH_SHIFT;
1477-
}
1478-
1479-
/*
1480-
* Gets device hardware parameters. Forces device mode if not
1481-
* currently in device mode. Should be called immediately after a core
1482-
* soft reset in order to get the reset values.
1483-
*/
1484-
static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
1485-
{
1486-
struct dwc2_hw_params *hw = &hsotg->hw_params;
1487-
bool forced;
1488-
u32 gnptxfsiz;
1489-
1490-
if (hsotg->dr_mode == USB_DR_MODE_HOST)
1491-
return;
1492-
1493-
forced = dwc2_force_mode_if_needed(hsotg, false);
1494-
1495-
gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1496-
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1497-
1498-
if (forced)
1499-
dwc2_clear_force_mode(hsotg);
1500-
1501-
hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1502-
FIFOSIZE_DEPTH_SHIFT;
1503-
}
1504-
15051407
/**
15061408
* During device initialization, read various hardware configuration
15071409
* registers and interpret the contents.
@@ -1511,7 +1413,8 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
15111413
struct dwc2_hw_params *hw = &hsotg->hw_params;
15121414
unsigned width;
15131415
u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
1514-
u32 grxfsiz;
1416+
u32 hptxfsiz, grxfsiz, gnptxfsiz;
1417+
u32 gusbcfg;
15151418

15161419
/*
15171420
* Attempt to ensure this device is really a DWC_otg Controller.
@@ -1543,16 +1446,20 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
15431446
dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
15441447
dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
15451448

1546-
/*
1547-
* Host specific hardware parameters. Reading these parameters
1548-
* requires the controller to be in host mode. The mode will
1549-
* be forced, if necessary, to read these values.
1550-
*/
1551-
dwc2_get_host_hwparams(hsotg);
1552-
dwc2_get_dev_hwparams(hsotg);
1449+
/* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
1450+
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
1451+
gusbcfg |= GUSBCFG_FORCEHOSTMODE;
1452+
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
1453+
usleep_range(100000, 150000);
15531454

1554-
/* hwcfg1 */
1555-
hw->dev_ep_dirs = hwcfg1;
1455+
gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
1456+
hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
1457+
dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
1458+
dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
1459+
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
1460+
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
1461+
dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
1462+
usleep_range(100000, 150000);
15561463

15571464
/* hwcfg2 */
15581465
hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
@@ -1582,6 +1489,13 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
15821489
width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
15831490
GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
15841491
hw->max_transfer_size = (1 << (width + 11)) - 1;
1492+
/*
1493+
* Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
1494+
* coherent buffers with this size, and if it's too large we can
1495+
* exhaust the coherent DMA pool.
1496+
*/
1497+
if (hw->max_transfer_size > 65535)
1498+
hw->max_transfer_size = 65535;
15851499
width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
15861500
GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
15871501
hw->max_packet_count = (1 << (width + 4)) - 1;
@@ -1601,6 +1515,10 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
16011515
/* fifo sizes */
16021516
hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
16031517
GRXFSIZ_DEPTH_SHIFT;
1518+
hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1519+
FIFOSIZE_DEPTH_SHIFT;
1520+
hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
1521+
FIFOSIZE_DEPTH_SHIFT;
16041522

16051523
dev_dbg(hsotg->dev, "Detected values from hardware:\n");
16061524
dev_dbg(hsotg->dev, " op_mode=%d\n",

‎drivers/usb/dwc2/core.h‎

Lines changed: 10 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,7 @@ struct dwc2_hsotg_ep {
221221
unsigned int target_frame;
222222
#define TARGET_FRAME_INITIAL 0xFFFFFFFF
223223
bool frame_overrun;
224+
unsigned int has_correct_parity:1;
224225

225226
char name[10];
226227
};
@@ -797,6 +798,7 @@ struct dwc2_hregs_backup {
797798
* @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
798799
* host is in high speed mode; low speed schedules are
799800
* stored elsewhere since we need one per TT.
801+
* @frame_usecs: Internal variable used by the microframe scheduler
800802
* @frame_number: Frame number read from the core at SOF. The value ranges
801803
* from 0 to HFNUM_MAX_FRNUM.
802804
* @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
@@ -874,6 +876,7 @@ struct dwc2_hsotg {
874876
int irq;
875877
struct clk *clks[DWC2_MAX_CLKS];
876878
struct reset_control *reset;
879+
struct clk *clk;
877880

878881
unsigned int queuing_high_bandwidth:1;
879882
unsigned int srp_success:1;
@@ -924,6 +927,7 @@ struct dwc2_hsotg {
924927
u16 periodic_usecs;
925928
unsigned long hs_periodic_bitmap[
926929
DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
930+
u16 frame_usecs[8];
927931
u16 frame_number;
928932
u16 periodic_qh_count;
929933
bool bus_suspended;
@@ -933,6 +937,7 @@ struct dwc2_hsotg {
933937

934938
#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
935939
#define FRAME_NUM_ARRAY_SIZE 1000
940+
u16 last_frame_num;
936941
u16 *frame_num_array;
937942
u16 *last_frame_num_array;
938943
int frame_num_idx;
@@ -1028,8 +1033,9 @@ enum dwc2_halt_status {
10281033
* The following functions support initialization of the core driver component
10291034
* and the DWC_otg controller
10301035
*/
1031-
extern int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1036+
extern int dwc2_core_reset(struct dwc2_hsotg *hsotg);
10321037
extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1038+
extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
10331039
extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
10341040
extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
10351041

@@ -1046,6 +1052,7 @@ extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
10461052
extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
10471053
extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
10481054

1055+
extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
10491056
extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
10501057
extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
10511058

@@ -1085,16 +1092,6 @@ extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
10851092
*/
10861093
extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
10871094

1088-
/*
1089-
* When DMA mode is enabled specifies whether to use
1090-
* address DMA or DMA Descritor mode with full speed devices
1091-
* for accessing the data FIFOs in host mode.
1092-
* 0 - address DMA
1093-
* 1 - FS DMA Descriptor(default, if available)
1094-
*/
1095-
extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg,
1096-
int val);
1097-
10981095
/*
10991096
* Specifies the maximum speed of operation in host and device mode.
11001097
* The actual speed depends on the speed of the attached device and
@@ -1339,20 +1336,14 @@ static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
13391336

13401337
#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
13411338
extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1342-
extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1343-
extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1344-
extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1339+
extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg);
13451340
extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
13461341
int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
13471342
int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
13481343
#else
13491344
static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
13501345
{ return 0; }
1351-
static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1352-
int us)
1353-
{ return 0; }
1354-
static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1355-
static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1346+
static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) {}
13561347
static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
13571348
static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
13581349
static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)

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