HDMI: waveshare 5 inch HDMI panel porting

if clock is not equal to request_clock in vop_crtc_mode_valid(),

check if request_clock is 33900 and match EDID,

then don't set mode to MODE_CLOCK_RANGE,

this solution is WAR

panel ID is DWE2100

Change-Id: Ie7edf81ffdac36ae35e888676dcf296cd6c4147b
Signed-off-by: bross1_kuo <bross1_kuo@asus.com>

Author: BrossKuo

drivers/gpu/drm/drm_edid.c

@@ -1279,6 +1279,10 @@ static const u8 asus_vz229h_edid[] = {
 static const u8 eve_vgg804838_edid[] = {
 	0x16, 0xC5, 0x01, 0x10
 };
+
+static const u8 dwe2100_edid[] = {
+	0x12, 0xE5, 0x00, 0x21
+};
 /**
  * drm_edid_header_is_valid - sanity check the header of the base EDID block
  * @raw_edid: pointer to raw base EDID block
@@ -1359,6 +1363,21 @@ bool drm_dect_eve_vgg804838_edid(struct edid *edid)
 }
 EXPORT_SYMBOL(drm_dect_eve_vgg804838_edid);
 
+bool drm_dect_dwe2100_edid(struct edid *edid)
+{
+	int i, score = 0;
+	u8 *raw_edid = (u8 *)edid;
+	for (i = 0; i < sizeof(dwe2100_edid); i++) {
+		if (raw_edid[8+i] == dwe2100_edid[i])
+			score++;
+	}
+	if (score == 4)
+		return true;
+	else
+		return false;
+}
+EXPORT_SYMBOL(drm_dect_dwe2100_edid);
+
 static int edid_fixup __read_mostly = 6;
 module_param_named(edid_fixup, edid_fixup, int, 0400);
 MODULE_PARM_DESC(edid_fixup,

drivers/gpu/drm/drm_probe_helper.c

@@ -60,6 +60,7 @@ static bool drm_iex_monitor = false;
 static bool drm_acer_kg221q_monitor = false;
 static bool drm_asus_vz229h_monitor = false;
 static bool drm_eve_vgg804838_panel = false;
+static bool drm_dwe2100_panel = false;
 module_param_named(poll, drm_kms_helper_poll, bool, 0600);
 
 static enum drm_mode_status
@@ -237,6 +238,7 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect
 		if( (*connector_funcs->check_edid)(connector) ) {
 			edid_manufacturer = (struct edid *) connector->edid_blob_ptr->data;
 			drm_eve_vgg804838_panel = drm_dect_eve_vgg804838_edid(edid_manufacturer);
+			drm_dwe2100_panel = drm_dect_dwe2100_edid(edid_manufacturer);
 		}
 	}
 
@@ -312,6 +314,12 @@ bool detect_eve_vgg804838_panel (void)
 }
 EXPORT_SYMBOL(detect_eve_vgg804838_panel);
 
+bool detect_dwe2100_panel (void)
+{
+	return drm_dwe2100_panel;
+}
+EXPORT_SYMBOL(detect_dwe2100_panel);
+
 /**
  * drm_helper_probe_single_connector_modes - get complete set of display modes
  * @connector: connector to probe

drivers/gpu/drm/rockchip/rockchip_drm_vop.c

@@ -2305,8 +2305,10 @@ vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 	int request_clock = mode->clock;
 	int clock;
 	bool eve_vgg804838_panel = false;
+	bool dwe2100_panel = false;
 
 	eve_vgg804838_panel = detect_eve_vgg804838_panel();
+	dwe2100_panel = detect_dwe2100_panel();
 
 	if (mode->clock >= 300000)
 		return MODE_CLOCK_RANGE;
@@ -2329,7 +2331,7 @@ vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 	if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
 	    output_type == DRM_MODE_CONNECTOR_DisplayPort)
 		if (clock != request_clock) {
-			if(request_clock == 33260 && eve_vgg804838_panel) {
+			if((request_clock == 33260 && eve_vgg804838_panel) || (request_clock == 33900 && dwe2100_panel)) {
 				pr_err("%s: don't block pixel clock %d KHz", __func__, request_clock);
 				return MODE_OK;
 			}

include/drm/drm_crtc.h

@@ -2034,6 +2034,8 @@ extern bool drm_dect_acer_kg221q_edid(struct edid *edid);
 extern bool drm_dect_asus_vz229h_edid(struct edid *edid);
 extern bool drm_dect_eve_vgg804838_edid(struct edid *edid);
 extern bool detect_eve_vgg804838_panel(void);
+extern bool drm_dect_dwe2100_edid(struct edid *edid);
+extern bool detect_dwe2100_panel(void);
 extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
 				 bool *edid_corrupt);
 extern bool drm_edid_is_valid(struct edid *edid);