@@ -735,8 +735,8 @@ void phy_detach(struct phy_device *phydev)
735735 int i ;
736736
737737 phydev -> attached_dev -> phydev = NULL ;
738- phydev -> attached_dev = NULL ;
739738 phy_suspend (phydev );
739+ phydev -> attached_dev = NULL ;
740740
741741 /* If the device had no specific driver before (i.e. - it
742742 * was using the generic driver), we unbind the device
@@ -1226,7 +1226,70 @@ static int gen10g_config_init(struct phy_device *phydev)
12261226int genphy_suspend (struct phy_device * phydev )
12271227{
12281228 int value ;
1229+ struct net_device * ndev = phydev -> attached_dev ;
1230+
1231+ mutex_lock (& phydev -> lock );
1232+
1233+ //#if RTL8211E
1234+ #if 1
1235+ phy_write (phydev , 31 , 0x07 );
1236+ phy_write (phydev , 30 , 0x6e );
1237+
1238+ phy_write (phydev , 21 , ((u16 )ndev -> dev_addr [1 ] << 8 ) + ndev -> dev_addr [0 ]);
1239+ phy_write (phydev , 22 , ((u16 )ndev -> dev_addr [3 ] << 8 ) + ndev -> dev_addr [2 ]);
1240+ phy_write (phydev , 23 , ((u16 )ndev -> dev_addr [5 ] << 8 ) + ndev -> dev_addr [4 ]);
1241+
1242+ phy_write (phydev , 31 , 0x07 );
1243+ phy_write (phydev , 30 , 0x6d );
1244+ phy_write (phydev , 22 , 0x1fff );
1245+ value = phy_read (phydev , 22 );
1246+
1247+ phy_write (phydev , 31 , 0x07 );
1248+ phy_write (phydev , 30 , 0x6d );
1249+ phy_write (phydev , 21 , 0x1000 );
1250+ value = phy_read (phydev , 21 );
1251+
1252+ phy_write (phydev , 31 , 0x07 );
1253+ phy_write (phydev , 30 , 0x6d );
1254+ value = phy_read (phydev , 25 );
1255+ phy_write (phydev , 25 , value | 0x1 );
1256+
1257+ phy_write (phydev , 31 , 0x0 );
1258+ value = phy_read (phydev , 31 );
1259+ #endif
1260+
1261+ //#if RTL8211F
1262+ #if 0
1263+ //set INTB pin
1264+ phy_write (priv -> phydev , 31 , 0x0d40 );
1265+ value = phy_read (priv -> phydev , 22 );
1266+ phy_write (priv -> phydev , 22 , value | BIT (5 ));
1267+
1268+ //set MAC address
1269+ phy_write (priv -> phydev , 31 , 0x0d8c );
1270+ phy_write (priv -> phydev , 16 , ((u16 )ndev -> dev_addr [1 ] << 8 ) + ndev -> dev_addr [0 ]);
1271+ phy_write (priv -> phydev , 17 , ((u16 )ndev -> dev_addr [3 ] << 8 ) + ndev -> dev_addr [2 ]);
1272+ phy_write (priv -> phydev , 18 , ((u16 )ndev -> dev_addr [5 ] << 8 ) + ndev -> dev_addr [4 ]);
1273+
1274+ //set max packet length
1275+ phy_write (priv -> phydev , 31 , 0x0d8a );
1276+ phy_write (priv -> phydev , 17 , 0x9fff );
1277+
1278+ //enable wol event
1279+ phy_write (priv -> phydev , 31 , 0x0d8a );
1280+ phy_write (priv -> phydev , 16 , 0x1000 );
1281+
1282+ //disable rgmii pad
1283+ phy_write (priv -> phydev , 31 , 0x0d8a );
1284+ value = phy_read (priv -> phydev , 19 );
1285+ phy_write (priv -> phydev , 19 , value | BIT (15 ));
1286+
1287+ phy_write (priv -> phydev , 31 , 0xa42 );
1288+ #endif
1289+ mutex_unlock (& phydev -> lock );
12291290
1291+ return 0 ;
1292+ /*
12301293 mutex_lock(&phydev->lock);
12311294
12321295 value = phy_read(phydev, MII_BMCR);
@@ -1235,6 +1298,7 @@ int genphy_suspend(struct phy_device *phydev)
12351298 mutex_unlock(&phydev->lock);
12361299
12371300 return 0;
1301+ */
12381302}
12391303EXPORT_SYMBOL (genphy_suspend );
12401304
@@ -1247,6 +1311,60 @@ int genphy_resume(struct phy_device *phydev)
12471311{
12481312 int value ;
12491313
1314+ if (phydev -> suspended ) {
1315+ mutex_lock (& phydev -> lock );
1316+ //#if RTL8211E
1317+ #if 1
1318+ phy_write (phydev , 31 , 0x07 );
1319+ phy_write (phydev , 30 , 0x6d );
1320+ phy_write (phydev , 21 , 0x0 );
1321+ value = phy_read (phydev , 21 );
1322+
1323+ phy_write (phydev , 31 , 0x07 );
1324+ phy_write (phydev , 30 , 0x6d );
1325+ value = phy_read (phydev , 22 );
1326+ phy_write (phydev , 22 , value | BIT (15 ));
1327+ value = phy_read (phydev , 22 );
1328+
1329+ phy_write (phydev , 31 , 0x07 );
1330+ phy_write (phydev , 30 , 0x6d );
1331+ value = phy_read (phydev , 25 );
1332+ phy_write (phydev , 25 , value & (~(0x1 )));
1333+
1334+ phy_write (phydev , 31 , 0x0 );
1335+ value = phy_read (phydev , 31 );
1336+ #endif
1337+
1338+ //#if RTL8211F
1339+ #if 0
1340+ //disable wol event
1341+ phy_write (priv -> phydev , 31 , 0x0d8a );
1342+ phy_write (priv -> phydev , 16 , 0x0 );
1343+
1344+ //reset wol
1345+ phy_write (priv -> phydev , 31 , 0x0d8a );
1346+ value = phy_read (priv -> phydev , 17 );
1347+ phy_write (priv -> phydev , 17 , value & (~BIT (15 )));
1348+
1349+ //enable rgmii pad
1350+ phy_write (priv -> phydev , 31 , 0x0d8a );
1351+ value = phy_read (priv -> phydev , 19 );
1352+ phy_write (priv -> phydev , 19 , value & (~BIT (15 )));
1353+
1354+ //set INTB pin
1355+ phy_write (priv -> phydev , 31 , 0x0d40 );
1356+ value = phy_read (priv -> phydev , 22 );
1357+ phy_write (priv -> phydev , 22 , value & (~BIT (5 )));
1358+
1359+ phy_write (priv -> phydev , 31 , 0xa42 );
1360+ #endif
1361+ mutex_unlock (& phydev -> lock );
1362+
1363+ msleep (100 );
1364+
1365+ return 0 ;
1366+ }
1367+
12501368 mutex_lock (& phydev -> lock );
12511369
12521370 value = phy_read (phydev , MII_BMCR );
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