ARM: dts: rockchip: add the needed power domain node on rk3036

As the vpu needed handle the power domain for reset function, this patch
supported the vpu domain for rk3036 Socs.

Change-Id: I67ad6085e2eb9a213c364d58713f02cc78ce6849
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Author: Caesar-github

arch/arm/boot/dts/rk3036.dtsi

@@ -43,6 +43,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3036-cru.h>
+#include <dt-bindings/power/rk3036-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
 #include "skeleton.dtsi"
 
@@ -248,6 +249,7 @@
 		assigned-clocks = <&cru ACLK_VCODEC>;
 		assigned-clock-rates = <297000000>;
 		assigned-clock-parents = <&cru PLL_GPLL>;
+		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
@@ -259,6 +261,7 @@
 		interrupt-names = "irq_dec";
 		iommus = <&vpu_mmu>;
 		allocator = <1>;
+		power-domains = <&power RK3036_PD_VPU>;
 	};
 
 	vpu_mmu: iommu@10108800 {
@@ -267,6 +270,7 @@
 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "vpu_mmu";
 		#iommu-cells = <0>;
+		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
@@ -278,6 +282,7 @@
 		interrupt-names = "irq_dec";
 		allocator = <1>;
 		iommus = <&hevc_mmu>;
+		power-domains = <&power RK3036_PD_VPU>;
 	};
 
 	hevc_mmu: iommu@1010c440 {
@@ -286,6 +291,7 @@
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hevc_mmu";
 		#iommu-cells = <0>;
+		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
@@ -306,6 +312,7 @@
 		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
 			 <&cru SRST_HEVC>;
 		reset-names = "video_a", "video_h", "video";
+		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
@@ -486,6 +493,21 @@
 			mode-loader = <BOOT_BL_DOWNLOAD>;
 			mode-ums = <BOOT_UMS>;
 		};
+
+		power: power-controller {
+			compatible = "rockchip,rk3036-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_vpu@RK3036_PD_VPU {
+				reg = <RK3036_PD_VPU>;
+				clocks = <&cru ACLK_VCODEC>,
+					 <&cru HCLK_VCODEC>,
+					 <&cru ACLK_HEVC>;
+			};
+
+		};
 	};
 
 	acodec: acodec-ana@20030000 {