Skip to content

Commit 89c18f1

Browse files
thierryredinggregkh
authored andcommitted
usb: host: ehci-tegra: Grab the correct UTMI pads reset
commit f8a15a9650694feaa0dabf197b0c94d37cd3fb42 upstream. There are three EHCI controllers on Tegra SoCs, each with its own reset line. However, the first controller contains a set of UTMI configuration registers that are shared with its siblings. These registers will only be reset as part of the first controller's reset. For proper operation it must be ensured that the UTMI configuration registers are reset before any of the EHCI controllers are enabled, irrespective of the probe order. Commit a47cc24 ("USB: EHCI: tegra: Fix probe order issue leading to broken USB") introduced code that ensures the first controller is always reset before setting up any of the controllers, and is never again reset afterwards. This code, however, grabs the wrong reset. Each EHCI controller has two reset controls attached: 1) the USB controller reset and 2) the UTMI pads reset (really the first controller's reset). In order to reset the UTMI pads registers the code must grab the second reset, but instead it grabbing the first. Fixes: a47cc24 ("USB: EHCI: tegra: Fix probe order issue leading to broken USB") Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent e845e8b commit 89c18f1

1 file changed

Lines changed: 1 addition & 1 deletion

File tree

drivers/usb/host/ehci-tegra.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,7 @@ static int tegra_reset_usb_controller(struct platform_device *pdev)
8989
if (!usb1_reset_attempted) {
9090
struct reset_control *usb1_reset;
9191

92-
usb1_reset = of_reset_control_get(phy_np, "usb");
92+
usb1_reset = of_reset_control_get(phy_np, "utmi-pads");
9393
if (IS_ERR(usb1_reset)) {
9494
dev_warn(&pdev->dev,
9595
"can't get utmi-pads reset from the PHY\n");

0 commit comments

Comments
 (0)