Skip to content

Commit 921a4f7

Browse files
SuperDavidWuSuperDavidWu
committed
pinctrl: rockchip: Add px30 pinctrl support
The bank0 of px30 pinctrl is in the pmugrf, other banks are in the grf, the bank1 ~ bank3 are 4-bit width's iomux. Change-Id: I62cbd74105b6874a9a91f3ab6a7623990205edce Signed-off-by: David Wu <david.wu@rock-chips.com>
1 parent 4178a29 commit 921a4f7

2 files changed

Lines changed: 197 additions & 0 deletions

File tree

‎Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ defined as gpio sub-nodes of the pinmux controller.
2020

2121
Required properties for iomux controller:
2222
- compatible: should be
23+
"rockchip,px30-pinctrl": for Rockchip PX30
2324
"rockchip,rk2928-pinctrl": for Rockchip RK2928
2425
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
2526
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b

‎drivers/pinctrl/pinctrl-rockchip.c‎

Lines changed: 196 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@
5959
#define GPIO_LS_SYNC 0x60
6060

6161
enum rockchip_pinctrl_type {
62+
PX30,
6263
RK2928,
6364
RK3066B,
6465
RK3128,
@@ -699,6 +700,66 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
699700
*bit = data->bit;
700701
}
701702

703+
static struct rockchip_mux_route_data px30_mux_route_data[] = {
704+
{
705+
/* cif-d2m0 */
706+
.bank_num = 2,
707+
.pin = 0,
708+
.func = 1,
709+
.route_offset = 0x184,
710+
.route_val = BIT(16 + 7),
711+
}, {
712+
/* cif-d2m1 */
713+
.bank_num = 3,
714+
.pin = 3,
715+
.func = 3,
716+
.route_offset = 0x184,
717+
.route_val = BIT(16 + 7) | BIT(7),
718+
}, {
719+
/* pdm-m0 */
720+
.bank_num = 3,
721+
.pin = 22,
722+
.func = 2,
723+
.route_offset = 0x184,
724+
.route_val = BIT(16 + 8),
725+
}, {
726+
/* pdm-m1 */
727+
.bank_num = 2,
728+
.pin = 22,
729+
.func = 1,
730+
.route_offset = 0x184,
731+
.route_val = BIT(16 + 8) | BIT(8),
732+
}, {
733+
/* uart2-rxm0 */
734+
.bank_num = 1,
735+
.pin = 26,
736+
.func = 2,
737+
.route_offset = 0x184,
738+
.route_val = BIT(16 + 9),
739+
}, {
740+
/* uart2-rxm1 */
741+
.bank_num = 2,
742+
.pin = 14,
743+
.func = 2,
744+
.route_offset = 0x184,
745+
.route_val = BIT(16 + 9) | BIT(9),
746+
}, {
747+
/* uart3-rxm0 */
748+
.bank_num = 0,
749+
.pin = 17,
750+
.func = 2,
751+
.route_offset = 0x184,
752+
.route_val = BIT(16 + 10),
753+
}, {
754+
/* uart3-rxm1 */
755+
.bank_num = 1,
756+
.pin = 13,
757+
.func = 2,
758+
.route_offset = 0x184,
759+
.route_val = BIT(16 + 10) | BIT(10),
760+
},
761+
};
762+
702763
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
703764
{
704765
/* spi-0 */
@@ -1182,6 +1243,69 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
11821243
return ret;
11831244
}
11841245

1246+
#define PX30_PULL_PMU_OFFSET 0x10
1247+
#define PX30_PULL_GRF_OFFSET 0x60
1248+
#define PX30_PULL_BITS_PER_PIN 2
1249+
#define PX30_PULL_PINS_PER_REG 8
1250+
#define PX30_PULL_BANK_STRIDE 16
1251+
1252+
static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1253+
int pin_num, struct regmap **regmap,
1254+
int *reg, u8 *bit)
1255+
{
1256+
struct rockchip_pinctrl *info = bank->drvdata;
1257+
1258+
/* The first 32 pins of the first bank are located in PMU */
1259+
if (bank->bank_num == 0) {
1260+
*regmap = info->regmap_pmu;
1261+
*reg = PX30_PULL_PMU_OFFSET;
1262+
} else {
1263+
*regmap = info->regmap_base;
1264+
*reg = PX30_PULL_GRF_OFFSET;
1265+
1266+
/* correct the offset, as we're starting with the 2nd bank */
1267+
*reg -= 0x10;
1268+
*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1269+
}
1270+
1271+
*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1272+
*bit = (pin_num % PX30_PULL_PINS_PER_REG);
1273+
*bit *= PX30_PULL_BITS_PER_PIN;
1274+
}
1275+
1276+
#define PX30_DRV_PMU_OFFSET 0x20
1277+
#define PX30_DRV_GRF_OFFSET 0xf0
1278+
#define PX30_DRV_BITS_PER_PIN 2
1279+
#define PX30_DRV_PINS_PER_REG 8
1280+
#define PX30_DRV_BANK_STRIDE 16
1281+
1282+
static enum rockchip_pin_drv_type px30_calc_drv_reg_and_bit(
1283+
struct rockchip_pin_bank *bank,
1284+
int pin_num, struct regmap **regmap,
1285+
int *reg, u8 *bit)
1286+
{
1287+
struct rockchip_pinctrl *info = bank->drvdata;
1288+
1289+
/* The first 32 pins of the first bank are located in PMU */
1290+
if (bank->bank_num == 0) {
1291+
*regmap = info->regmap_pmu;
1292+
*reg = PX30_DRV_PMU_OFFSET;
1293+
} else {
1294+
*regmap = info->regmap_base;
1295+
*reg = PX30_DRV_GRF_OFFSET;
1296+
1297+
/* correct the offset, as we're starting with the 2nd bank */
1298+
*reg -= 0x10;
1299+
*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1300+
}
1301+
1302+
*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1303+
*bit = (pin_num % PX30_DRV_PINS_PER_REG);
1304+
*bit *= PX30_DRV_BITS_PER_PIN;
1305+
1306+
return DRV_TYPE_IO_DEFAULT;
1307+
}
1308+
11851309
#define RK2928_PULL_OFFSET 0x118
11861310
#define RK2928_PULL_PINS_PER_REG 16
11871311
#define RK2928_PULL_BANK_STRIDE 8
@@ -1959,6 +2083,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
19592083
return !(data & BIT(bit))
19602084
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
19612085
: PIN_CONFIG_BIAS_DISABLE;
2086+
case PX30:
19622087
case RK3188:
19632088
case RK3288:
19642089
case RK3366:
@@ -2002,6 +2127,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
20022127
data |= BIT(bit);
20032128
ret = regmap_write(regmap, reg, data);
20042129
break;
2130+
case PX30:
20052131
case RK3188:
20062132
case RK3288:
20072133
case RK3366:
@@ -2037,6 +2163,36 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
20372163
return ret;
20382164
}
20392165

2166+
#define PX30_SCHMITT_PMU_OFFSET 0x38
2167+
#define PX30_SCHMITT_GRF_OFFSET 0xc0
2168+
#define PX30_SCHMITT_PINS_PER_PMU_REG 16
2169+
#define PX30_SCHMITT_BANK_STRIDE 16
2170+
#define PX30_SCHMITT_PINS_PER_GRF_REG 8
2171+
2172+
static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2173+
int pin_num,
2174+
struct regmap **regmap,
2175+
int *reg, u8 *bit)
2176+
{
2177+
struct rockchip_pinctrl *info = bank->drvdata;
2178+
int pins_per_reg;
2179+
2180+
if (bank->bank_num == 0) {
2181+
*regmap = info->regmap_pmu;
2182+
*reg = PX30_SCHMITT_PMU_OFFSET;
2183+
pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
2184+
} else {
2185+
*regmap = info->regmap_base;
2186+
*reg = PX30_SCHMITT_GRF_OFFSET;
2187+
pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
2188+
*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
2189+
}
2190+
*reg += ((pin_num / pins_per_reg) * 4);
2191+
*bit = pin_num % pins_per_reg;
2192+
2193+
return 0;
2194+
}
2195+
20402196
#define RK3328_SCHMITT_BITS_PER_PIN 1
20412197
#define RK3328_SCHMITT_PINS_PER_REG 16
20422198
#define RK3328_SCHMITT_BANK_STRIDE 8
@@ -2245,6 +2401,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
22452401
pull == PIN_CONFIG_BIAS_DISABLE);
22462402
case RK3066B:
22472403
return pull ? false : true;
2404+
case PX30:
22482405
case RK3188:
22492406
case RK3288:
22502407
case RK3366:
@@ -3383,6 +3540,43 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
33833540
return 0;
33843541
}
33853542

3543+
static struct rockchip_pin_bank px30_pin_banks[] = {
3544+
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3545+
IOMUX_SOURCE_PMU,
3546+
IOMUX_SOURCE_PMU,
3547+
IOMUX_SOURCE_PMU
3548+
),
3549+
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3550+
IOMUX_WIDTH_4BIT,
3551+
IOMUX_WIDTH_4BIT,
3552+
IOMUX_WIDTH_4BIT
3553+
),
3554+
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3555+
IOMUX_WIDTH_4BIT,
3556+
IOMUX_WIDTH_4BIT,
3557+
IOMUX_WIDTH_4BIT
3558+
),
3559+
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3560+
IOMUX_WIDTH_4BIT,
3561+
IOMUX_WIDTH_4BIT,
3562+
IOMUX_WIDTH_4BIT
3563+
),
3564+
};
3565+
3566+
static struct rockchip_pin_ctrl px30_pin_ctrl = {
3567+
.pin_banks = px30_pin_banks,
3568+
.nr_banks = ARRAY_SIZE(px30_pin_banks),
3569+
.label = "PX30-GPIO",
3570+
.type = PX30,
3571+
.grf_mux_offset = 0x0,
3572+
.pmu_mux_offset = 0x0,
3573+
.iomux_routes = px30_mux_route_data,
3574+
.niomux_routes = ARRAY_SIZE(px30_mux_route_data),
3575+
.pull_calc_reg = px30_calc_pull_reg_and_bit,
3576+
.drv_calc_reg = px30_calc_drv_reg_and_bit,
3577+
.schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
3578+
};
3579+
33863580
static struct rockchip_pin_bank rk2928_pin_banks[] = {
33873581
PIN_BANK(0, 32, "gpio0"),
33883582
PIN_BANK(1, 32, "gpio1"),
@@ -3727,6 +3921,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
37273921
};
37283922

37293923
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3924+
{ .compatible = "rockchip,px30-pinctrl",
3925+
.data = &px30_pin_ctrl },
37303926
{ .compatible = "rockchip,rk2928-pinctrl",
37313927
.data = &rk2928_pin_ctrl },
37323928
{ .compatible = "rockchip,rk3036-pinctrl",

0 commit comments

Comments
 (0)