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phy: rockchip: mipi-dphy-tx1rx1: add mipi-dphy TX1RX1 channel for RK3288
This patch adds the function of mipi-dphy TX1RX1 for RK3288, the mipi-dphy TX1RX1 is matched when "txrx_base_addr" is valid. Change-Id: I01640925157a7082e942188b29f6bbf1318cf3d5 Signed-off-by: Wen Nuan <leo.wen@rock-chips.com>
1 parent 67217a7 commit ad46e68

2 files changed

Lines changed: 174 additions & 61 deletions

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‎Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,12 @@ Required properties:
1111

1212
MIPI RX0 D-PHY use registers in "general register files", it
1313
should be a child of the GRF.
14-
MIPI TXRX D-PHY have its own registers, it must have a reg property.
14+
MIPI TX1RX1 D-PHY have its own registers, it must have a reg property.
1515

1616
Optional properties:
1717
- reg: offset and length of the register set for the device.
18+
- rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also
19+
the GRF, so it is only necessary for MIPI TX1RX1 D-PHY.
1820

1921
port node
2022
-------------------

‎drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c‎

Lines changed: 171 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,21 @@
6868
#define LANE1_HS_RX_CONTROL 0x54
6969
#define LANE2_HS_RX_CONTROL 0x84
7070
#define LANE3_HS_RX_CONTROL 0x94
71-
#define HS_RX_DATA_LANES_THS_SETTLE__CONTROL 0x75
71+
#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75
72+
73+
/*
74+
* CSI HOST
75+
*/
76+
#define CSIHOST_PHY_TEST_CTRL0 0x30
77+
#define CSIHOST_PHY_TEST_CTRL1 0x34
78+
#define CSIHOST_PHY_SHUTDOWNZ 0x08
79+
#define CSIHOST_DPHY_RSTZ 0x0c
80+
81+
#define PHY_TESTEN_ADDR (0x1 << 16)
82+
#define PHY_TESTEN_DATA (0x0 << 16)
83+
#define PHY_TESTCLK (0x1 << 1)
84+
#define PHY_TESTCLR (0x1 << 0)
85+
#define THS_SETTLE_COUNTER_THRESHOLD 0x04
7286

7387
#define HIWORD_UPDATE(val, mask, shift) \
7488
((val) << (shift) | (mask) << ((shift) + 16))
@@ -185,6 +199,8 @@ struct hsfreq_range {
185199
u8 cfg_bit;
186200
};
187201

202+
struct mipidphy_priv;
203+
188204
struct dphy_drv_data {
189205
const char * const *clks;
190206
int num_clks;
@@ -221,14 +237,17 @@ struct mipidphy_priv {
221237
struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
222238
int num_sensors;
223239
bool is_streaming;
240+
void __iomem *txrx_base_addr;
241+
int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
224242
};
225243

226244
static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
227245
{
228246
return container_of(subdev, struct mipidphy_priv, sd);
229247
}
230248

231-
static inline void write_reg(struct mipidphy_priv *priv, int index, u8 value)
249+
static inline void write_grf_reg(struct mipidphy_priv *priv,
250+
int index, u8 value)
232251
{
233252
const struct dphy_reg *reg = &priv->grf_regs[index];
234253
unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
@@ -237,21 +256,38 @@ static inline void write_reg(struct mipidphy_priv *priv, int index, u8 value)
237256
regmap_write(priv->regmap_grf, reg->offset, val);
238257
}
239258

240-
static void mipidphy_wr_reg(struct mipidphy_priv *priv,
241-
u8 test_code, u8 test_data)
259+
static void mipidphy0_wr_reg(struct mipidphy_priv *priv,
260+
u8 test_code, u8 test_data)
242261
{
243262
/*
244263
* With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
245264
* is latched internally as the current test code. Test data is
246265
* programmed internally by rising edge on TESTCLK.
247266
*/
248-
write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
249-
write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
250-
write_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
251-
write_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
252-
write_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
253-
write_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
254-
write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
267+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
268+
write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
269+
write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
270+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
271+
write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
272+
write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
273+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
274+
}
275+
276+
static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
277+
unsigned char data)
278+
{
279+
/*
280+
* TESTEN =1,TESTDIN=addr
281+
* TESTCLK=0
282+
* TESTEN =0,TESTDIN=data
283+
* TESTCLK=1
284+
*/
285+
writel((PHY_TESTEN_ADDR | addr),
286+
priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL1);
287+
writel(0x00, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
288+
writel((PHY_TESTEN_DATA | data),
289+
priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL1);
290+
writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
255291
}
256292

257293
static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
@@ -316,12 +352,7 @@ static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
316352
static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
317353
{
318354
struct mipidphy_priv *priv = to_dphy_priv(sd);
319-
const struct dphy_drv_data *drv_data = priv->drv_data;
320-
const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
321-
int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
322-
struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
323-
struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
324-
int i, ret, hsfreq = 0;
355+
int ret = 0;
325356

326357
if (priv->is_streaming)
327358
return 0;
@@ -330,44 +361,7 @@ static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
330361
if (ret < 0)
331362
return ret;
332363

333-
for (i = 0; i < num_hsfreq_ranges; i++) {
334-
if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
335-
hsfreq = hsfreq_ranges[i].cfg_bit;
336-
break;
337-
}
338-
}
339-
340-
write_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
341-
write_reg(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
342-
/* Disable lan turn around, which is ignored in receive mode */
343-
write_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
344-
write_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
345-
346-
write_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
347-
348-
/* dphy start */
349-
write_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
350-
write_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
351-
usleep_range(100, 150);
352-
write_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
353-
usleep_range(100, 150);
354-
355-
/* set clock lane */
356-
/* HS hsfreq_range & lane 0 settle bypass */
357-
mipidphy_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
358-
/* HS RX Control of lane0 */
359-
mipidphy_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
360-
/* HS RX Control of lane1 */
361-
mipidphy_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
362-
/* HS RX Control of lane2 */
363-
mipidphy_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
364-
/* HS RX Control of lane3 */
365-
mipidphy_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
366-
/* HS RX Data Lanes Settle State Time Control */
367-
mipidphy_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE__CONTROL, 0x04);
368-
369-
/* Normal operation */
370-
mipidphy_wr_reg(priv, 0x0, 0);
364+
priv->stream_on(priv, sd);
371365

372366
priv->is_streaming = true;
373367

@@ -521,6 +515,112 @@ static const char * const rk3288_mipidphy_clks[] = {
521515
"pclk",
522516
};
523517

518+
static int mipidphy_rx_stream_on(struct mipidphy_priv *priv,
519+
struct v4l2_subdev *sd)
520+
{
521+
struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
522+
struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
523+
const struct dphy_drv_data *drv_data = priv->drv_data;
524+
const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
525+
int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
526+
int i, hsfreq = 0;
527+
528+
for (i = 0; i < num_hsfreq_ranges; i++) {
529+
if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
530+
hsfreq = hsfreq_ranges[i].cfg_bit;
531+
break;
532+
}
533+
}
534+
write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);
535+
write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
536+
write_grf_reg(priv, GRF_DPHY_RX0_FORCETXSTOPMODE, 0);
537+
/* Disable lan turn around, which is ignored in receive mode */
538+
write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
539+
write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
540+
541+
write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
542+
543+
/* dphy start */
544+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
545+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
546+
usleep_range(100, 150);
547+
write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
548+
usleep_range(100, 150);
549+
550+
/* set clock lane */
551+
/* HS hsfreq_range & lane 0 settle bypass */
552+
mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
553+
/* HS RX Control of lane0 */
554+
mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
555+
/* HS RX Control of lane1 */
556+
mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
557+
/* HS RX Control of lane2 */
558+
mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
559+
/* HS RX Control of lane3 */
560+
mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
561+
/* HS RX Data Lanes Settle State Time Control */
562+
mipidphy0_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE_CONTROL,
563+
THS_SETTLE_COUNTER_THRESHOLD);
564+
565+
/* Normal operation */
566+
mipidphy0_wr_reg(priv, 0x0, 0);
567+
568+
return 0;
569+
}
570+
571+
static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
572+
struct v4l2_subdev *sd)
573+
{
574+
struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
575+
struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd);
576+
const struct dphy_drv_data *drv_data = priv->drv_data;
577+
const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
578+
int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
579+
int i, hsfreq = 0;
580+
581+
for (i = 0; i < num_hsfreq_ranges; i++) {
582+
if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
583+
hsfreq = hsfreq_ranges[i].cfg_bit;
584+
break;
585+
}
586+
}
587+
write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);
588+
write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);
589+
write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);
590+
write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
591+
write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);
592+
/* Disable lan turn around, which is ignored in receive mode */
593+
write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);
594+
write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);
595+
write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);
596+
write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);
597+
write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE,
598+
GENMASK(sensor->lanes - 1, 0));
599+
/* dphy start */
600+
writel(0, priv->txrx_base_addr + CSIHOST_PHY_SHUTDOWNZ);
601+
writel(0, priv->txrx_base_addr + CSIHOST_DPHY_RSTZ);
602+
writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
603+
writel(PHY_TESTCLR, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
604+
usleep_range(100, 150);
605+
writel(PHY_TESTCLK, priv->txrx_base_addr + CSIHOST_PHY_TEST_CTRL0);
606+
usleep_range(100, 150);
607+
608+
/* set clock lane */
609+
mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
610+
mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq << 1);
611+
mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
612+
mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
613+
mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
614+
/* HS RX Data Lanes Settle State Time Control */
615+
mipidphy1_wr_reg(priv, HS_RX_DATA_LANES_THS_SETTLE_CONTROL,
616+
THS_SETTLE_COUNTER_THRESHOLD);
617+
618+
/* Normal operation */
619+
mipidphy1_wr_reg(priv, 0x0, 0);
620+
621+
return 0;
622+
}
623+
524624
static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
525625
.clks = rk3288_mipidphy_clks,
526626
.num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
@@ -620,8 +720,8 @@ v4l2_async_notifier_operations rockchip_mipidphy_async_ops = {
620720
};
621721

622722
static int rockchip_mipidphy_fwnode_parse(struct device *dev,
623-
struct v4l2_fwnode_endpoint *vep,
624-
struct v4l2_async_subdev *asd)
723+
struct v4l2_fwnode_endpoint *vep,
724+
struct v4l2_async_subdev *asd)
625725
{
626726
struct sensor_async_subdev *s_asd =
627727
container_of(asd, struct sensor_async_subdev, asd);
@@ -671,7 +771,7 @@ static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
671771
MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
672772

673773
ret = media_entity_init(&priv->sd.entity,
674-
MIPI_DPHY_SY_PADS_NUM, priv->pads, 0);
774+
MIPI_DPHY_SY_PADS_NUM, priv->pads, 0);
675775
if (ret < 0)
676776
return ret;
677777

@@ -704,6 +804,7 @@ static int rockchip_mipidphy_probe(struct platform_device *pdev)
704804
struct v4l2_subdev *sd;
705805
struct mipidphy_priv *priv;
706806
struct regmap *grf;
807+
struct resource *res;
707808
const struct of_device_id *of_id;
708809
const struct dphy_drv_data *drv_data;
709810
int i, ret;
@@ -719,8 +820,12 @@ static int rockchip_mipidphy_probe(struct platform_device *pdev)
719820

720821
grf = syscon_node_to_regmap(dev->parent->of_node);
721822
if (IS_ERR(grf)) {
722-
dev_err(dev, "Can't find GRF syscon\n");
723-
return -ENODEV;
823+
grf = syscon_regmap_lookup_by_phandle(dev->of_node,
824+
"rockchip,grf");
825+
if (IS_ERR(grf)) {
826+
dev_err(dev, "Can't find GRF syscon\n");
827+
return -ENODEV;
828+
}
724829
}
725830
priv->regmap_grf = grf;
726831

@@ -736,6 +841,12 @@ static int rockchip_mipidphy_probe(struct platform_device *pdev)
736841

737842
priv->grf_regs = drv_data->regs;
738843
priv->drv_data = drv_data;
844+
priv->stream_on = mipidphy_txrx_stream_on;
845+
priv->txrx_base_addr = NULL;
846+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847+
priv->txrx_base_addr = devm_ioremap_resource(dev, res);
848+
if (IS_ERR(priv->txrx_base_addr))
849+
priv->stream_on = mipidphy_rx_stream_on;
739850

740851
sd = &priv->sd;
741852
v4l2_subdev_init(sd, &mipidphy_subdev_ops);

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