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Yu Qiaoweirkhuangtao
Yu Qiaowei
authored and
rkhuangtao
committed
video/rockchip: rga2: Add invalidate cache.
Use dma_map_page/dma_unmap_page to flush cache.Users need to call rga2_blit_flush_cache() to flush cache according to their needs. Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com> Change-Id: Ic929d3d4e5c1d23fae542481ca90ab6ba1680e0e
1 parent 8914a48 commit ae13119

4 files changed

Lines changed: 157 additions & 14 deletions

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‎drivers/video/rockchip/rga2/rga2.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -682,6 +682,7 @@ struct rga2_reg {
682682

683683
uint32_t *MMU_base;
684684
uint32_t MMU_len;
685+
bool MMU_map;
685686

686687
struct sg_table *sg_src0;
687688
struct sg_table *sg_src1;

‎drivers/video/rockchip/rga2/rga2_drv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,6 +1421,7 @@ static int rga2_blit_flush_cache(rga2_session *session, struct rga2_req *req)
14211421
#endif
14221422
if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) ||
14231423
(req->mmu_info.dst_mmu_flag & 1) || (req->mmu_info.els_mmu_flag & 1)) {
1424+
reg->MMU_map = true;
14241425
ret = rga2_set_mmu_info(reg, req);
14251426
if (ret < 0) {
14261427
pr_err("%s, [%d] set mmu info error\n", __func__, __LINE__);

‎drivers/video/rockchip/rga2/rga2_mmu_info.c‎

Lines changed: 146 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -43,13 +43,47 @@ void rga2_dma_flush_range(void *pstart, void *pend)
4343
dma_sync_single_for_device(rga2_drvdata->dev, virt_to_phys(pstart), pend - pstart, DMA_TO_DEVICE);
4444
}
4545

46-
static void rga2_dma_flush_page(struct page *page)
46+
static void rga2_dma_flush_page(struct page *page, int map)
4747
{
48-
phys_addr_t paddr;
48+
dma_addr_t paddr;
4949

5050
paddr = page_to_phys(page);
5151

52-
dma_sync_single_for_device(rga2_drvdata->dev, paddr, PAGE_SIZE, DMA_TO_DEVICE);
52+
if (map & MMU_MAP_MASK) {
53+
switch (map) {
54+
case MMU_MAP_CLEAN:
55+
dma_map_page(rga2_drvdata->dev, page, 0,
56+
PAGE_SIZE, DMA_TO_DEVICE);
57+
break;
58+
case MMU_MAP_INVALID:
59+
dma_map_page(rga2_drvdata->dev, page, 0,
60+
PAGE_SIZE, DMA_FROM_DEVICE);
61+
break;
62+
case MMU_MAP_CLEAN | MMU_MAP_INVALID:
63+
dma_map_page(rga2_drvdata->dev, page, 0,
64+
PAGE_SIZE, DMA_TO_DEVICE);
65+
dma_map_page(rga2_drvdata->dev, page, 0,
66+
PAGE_SIZE, DMA_FROM_DEVICE);
67+
break;
68+
}
69+
} else if (map & MMU_UNMAP_MASK) {
70+
switch (map) {
71+
case MMU_UNMAP_CLEAN:
72+
dma_unmap_page(rga2_drvdata->dev, paddr,
73+
PAGE_SIZE, DMA_TO_DEVICE);
74+
break;
75+
case MMU_UNMAP_INVALID:
76+
dma_unmap_page(rga2_drvdata->dev, paddr,
77+
PAGE_SIZE, DMA_FROM_DEVICE);
78+
break;
79+
case MMU_UNMAP_CLEAN | MMU_UNMAP_INVALID:
80+
dma_unmap_page(rga2_drvdata->dev, paddr,
81+
PAGE_SIZE, DMA_TO_DEVICE);
82+
dma_unmap_page(rga2_drvdata->dev, paddr,
83+
PAGE_SIZE, DMA_FROM_DEVICE);
84+
break;
85+
}
86+
}
5387
}
5488

5589
#if 0
@@ -382,7 +416,7 @@ static int rga2_UserMemory_cheeck(struct page **pages, u32 w, u32 h, u32 format,
382416

383417
static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
384418
unsigned long Memory, uint32_t pageCount,
385-
int writeFlag)
419+
int writeFlag, int map)
386420
{
387421
struct vm_area_struct *vma;
388422
int32_t result;
@@ -417,7 +451,7 @@ static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
417451
for (i = 0; i < pageCount; i++) {
418452
/* Get the physical address from page struct. */
419453
pageTable[i] = page_to_phys(pages[i]);
420-
rga2_dma_flush_page(pages[i]);
454+
rga2_dma_flush_page(pages[i], map);
421455
}
422456
for (i = 0; i < result; i++)
423457
put_page(pages[i]);
@@ -465,7 +499,7 @@ static int rga2_MapUserMemory(struct page **pages, uint32_t *pageTable,
465499
Address = ((pfn << PAGE_SHIFT) | (((unsigned long)((Memory + i)
466500
<< PAGE_SHIFT)) & ~PAGE_MASK));
467501
pageTable[i] = (uint32_t)Address;
468-
rga2_dma_flush_page(pfn_to_page(pfn));
502+
rga2_dma_flush_page(pfn_to_page(pfn), map);
469503
pte_unmap_unlock(pte, ptl);
470504
}
471505
up_read(&current->mm->mmap_sem);
@@ -508,6 +542,80 @@ static int rga2_MapION(struct sg_table *sg,
508542
return 0;
509543
}
510544

545+
static int rga2_mmu_flush_cache(struct rga2_reg *reg, struct rga2_req *req)
546+
{
547+
int DstMemSize;
548+
unsigned long DstStart, DstPageCount;
549+
uint32_t *MMU_Base, *MMU_Base_phys;
550+
int ret;
551+
int status;
552+
struct page **pages = NULL;
553+
554+
MMU_Base = NULL;
555+
DstMemSize = 0;
556+
DstPageCount = 0;
557+
DstStart = 0;
558+
559+
if (reg->MMU_map != true)
560+
goto out;
561+
562+
/* cal dst buf mmu info */
563+
if (req->mmu_info.dst_mmu_flag & 1) {
564+
DstPageCount = rga2_buf_size_cal(req->dst.yrgb_addr,
565+
req->dst.uv_addr,
566+
req->dst.v_addr,
567+
req->dst.format,
568+
req->dst.vir_w,
569+
req->dst.vir_h,
570+
&DstStart);
571+
if (DstPageCount == 0)
572+
return -EINVAL;
573+
}
574+
/* Cal out the needed mem size */
575+
DstMemSize = (DstPageCount + 15) & (~15);
576+
577+
if (rga2_mmu_buf_get_try(&rga2_mmu_buf, DstMemSize)) {
578+
pr_err("RGA2 Get MMU mem failed\n");
579+
status = RGA2_MALLOC_ERROR;
580+
goto out;
581+
}
582+
pages = rga2_mmu_buf.pages;
583+
mutex_lock(&rga2_service.lock);
584+
MMU_Base = rga2_mmu_buf.buf_virtual +
585+
(rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));
586+
MMU_Base_phys = rga2_mmu_buf.buf +
587+
(rga2_mmu_buf.front & (rga2_mmu_buf.size - 1));
588+
589+
mutex_unlock(&rga2_service.lock);
590+
if (DstMemSize) {
591+
if (req->sg_dst) {
592+
goto out;
593+
} else {
594+
ret = rga2_MapUserMemory(&pages[0],
595+
MMU_Base,
596+
DstStart, DstPageCount, 1,
597+
MMU_MAP_CLEAN | MMU_MAP_INVALID);
598+
#if RGA2_DEBUGFS
599+
if (RGA2_CHECK_MODE)
600+
rga2_UserMemory_cheeck(&pages[0],
601+
req->dst.vir_w,
602+
req->dst.vir_h,
603+
req->dst.format,
604+
2);
605+
#endif
606+
}
607+
if (ret < 0) {
608+
pr_err("rga2 unmap dst memory failed\n");
609+
status = ret;
610+
goto out;
611+
}
612+
}
613+
rga2_mmu_buf_get(&rga2_mmu_buf, DstMemSize);
614+
reg->MMU_len = DstMemSize;
615+
status = 0;
616+
out:
617+
return status;
618+
}
511619

512620
static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
513621
{
@@ -593,7 +701,8 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
593701
&MMU_Base[0], Src0MemSize);
594702
} else {
595703
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
596-
Src0Start, Src0PageCount, 0);
704+
Src0Start, Src0PageCount,
705+
0, MMU_MAP_CLEAN);
597706
#if RGA2_DEBUGFS
598707
if (RGA2_CHECK_MODE)
599708
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
@@ -627,7 +736,8 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
627736
else
628737
ret = rga2_MapUserMemory(&pages[0],
629738
MMU_Base + Src0MemSize,
630-
Src1Start, Src1PageCount, 0);
739+
Src1Start, Src1PageCount,
740+
0, MMU_MAP_CLEAN);
631741
if (ret < 0) {
632742
pr_err("rga2 map src1 memory failed\n");
633743
status = ret;
@@ -642,10 +752,25 @@ static int rga2_mmu_info_BitBlt_mode(struct rga2_reg *reg, struct rga2_req *req)
642752
if (req->sg_dst) {
643753
ret = rga2_MapION(req->sg_dst, MMU_Base + Src0MemSize
644754
+ Src1MemSize, DstMemSize);
755+
} else if (req->alpha_mode_0 != 0 && req->bitblt_mode == 0) {
756+
/* The blend mode of src + dst => dst requires clean and invalidate */
757+
ret = rga2_MapUserMemory(&pages[0], MMU_Base
758+
+ Src0MemSize + Src1MemSize,
759+
DstStart, DstPageCount, 1,
760+
MMU_MAP_CLEAN | MMU_MAP_INVALID);
761+
#if RGA2_DEBUGFS
762+
if (RGA2_CHECK_MODE)
763+
rga2_UserMemory_cheeck(&pages[0],
764+
req->src.vir_w,
765+
req->src.vir_h,
766+
req->src.format,
767+
2);
768+
#endif
645769
} else {
646770
ret = rga2_MapUserMemory(&pages[0], MMU_Base
647771
+ Src0MemSize + Src1MemSize,
648-
DstStart, DstPageCount, 1);
772+
DstStart, DstPageCount,
773+
1, MMU_MAP_INVALID);
649774
#if RGA2_DEBUGFS
650775
if (RGA2_CHECK_MODE)
651776
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
@@ -761,7 +886,7 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
761886
&MMU_Base[0], SrcMemSize);
762887
} else {
763888
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
764-
SrcStart, SrcMemSize, 0);
889+
SrcStart, SrcMemSize, 0, MMU_MAP_CLEAN);
765890
#if RGA2_DEBUGFS
766891
if (RGA2_CHECK_MODE)
767892
rga2_UserMemory_cheeck(&pages[0], req->src.vir_w,
@@ -786,7 +911,7 @@ static int rga2_mmu_info_color_palette_mode(struct rga2_reg *reg, struct rga2_re
786911
MMU_Base + SrcMemSize, DstMemSize);
787912
} else {
788913
ret = rga2_MapUserMemory(&pages[0], MMU_Base + SrcMemSize,
789-
DstStart, DstMemSize, 1);
914+
DstStart, DstMemSize, 1, MMU_MAP_INVALID);
790915
#if RGA2_DEBUGFS
791916
if (RGA2_CHECK_MODE)
792917
rga2_UserMemory_cheeck(&pages[0], req->dst.vir_w,
@@ -860,7 +985,8 @@ static int rga2_mmu_info_color_fill_mode(struct rga2_reg *reg, struct rga2_req *
860985
}
861986
else {
862987
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
863-
DstStart, DstMemSize, 1);
988+
DstStart, DstMemSize,
989+
1, MMU_MAP_INVALID);
864990
}
865991
if (ret < 0) {
866992
pr_err("rga2 map dst memory failed\n");
@@ -940,7 +1066,7 @@ static int rga2_mmu_info_update_palette_table_mode(struct rga2_reg *reg, struct
9401066
&MMU_Base[0], LutMemSize);
9411067
} else {
9421068
ret = rga2_MapUserMemory(&pages[0], &MMU_Base[0],
943-
LutStart, LutMemSize, 0);
1069+
LutStart, LutMemSize, 0, MMU_MAP_CLEAN);
9441070
}
9451071
if (ret < 0) {
9461072
pr_err("rga2 map palette memory failed\n");
@@ -1005,7 +1131,8 @@ static int rga2_mmu_info_update_patten_buff_mode(struct rga2_reg *reg, struct rg
10051131
{
10061132
ret = rga2_MapUserMemory(&pages[CMDMemSize],
10071133
&MMU_Base[CMDMemSize],
1008-
SrcStart, SrcMemSize, 1);
1134+
SrcStart, SrcMemSize,
1135+
1, MMU_MAP_CLEAN);
10091136
if (ret < 0) {
10101137
pr_err("rga map src memory failed\n");
10111138
status = ret;
@@ -1047,6 +1174,11 @@ int rga2_set_mmu_info(struct rga2_reg *reg, struct rga2_req *req)
10471174
{
10481175
int ret;
10491176

1177+
if (reg->MMU_map == true) {
1178+
ret = rga2_mmu_flush_cache(reg, req);
1179+
return ret;
1180+
}
1181+
10501182
switch (req->render_mode) {
10511183
case bitblt_mode :
10521184
ret = rga2_mmu_info_BitBlt_mode(reg, req);

‎drivers/video/rockchip/rga2/rga2_mmu_info.h‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,15 @@
1515

1616
extern struct rga2_drvdata_t *rga2_drvdata;
1717

18+
enum {
19+
MMU_MAP_CLEAN = 1 << 0,
20+
MMU_MAP_INVALID = 1 << 1,
21+
MMU_MAP_MASK = 0x03,
22+
MMU_UNMAP_CLEAN = 1 << 2,
23+
MMU_UNMAP_INVALID = 1 << 3,
24+
MMU_UNMAP_MASK = 0x0c,
25+
};
26+
1827
int rga2_set_mmu_info(struct rga2_reg *reg, struct rga2_req *req);
1928
void rga2_dma_flush_range(void *pstart, void *pend);
2029

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