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mathieupoiriermathieupoirier
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coresight: etb10: splitting sysFS "status" entry
The sysFS "status" entry conveys a wealth of information about the status of the HW but goes agains the sysFS rule of one topic per file. This patch rectify the situation by adding read-only entries for each of the field formaly displayed by "status". The ABI documentation is kept up to date. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit ad352acbb9d606a5facff31fd96b05d0346726b1)
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Lines changed: 100 additions & 50 deletions

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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-etb10‎

Lines changed: 62 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,6 @@ Description: (RW) Add/remove a sink from a trace path. There can be multiple
66
source for a single sink.
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ex: echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
88

9-
What: /sys/bus/coresight/devices/<memory_map>.etb/status
10-
Date: November 2014
11-
KernelVersion: 3.19
12-
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
13-
Description: (R) List various control and status registers. The specific
14-
layout and content is driver specific.
15-
169
What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
1710
Date: November 2014
1811
KernelVersion: 3.19
@@ -22,3 +15,65 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
2215
following the trigger event. The number of 32-bit words written
2316
into the Trace RAM following the trigger event is equal to the
2417
value stored in this register+1 (from ARM ETB-TRM).
18+
19+
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
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Date: March 2016
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KernelVersion: 4.7
22+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Defines the depth, in words, of the trace RAM in powers of
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2. The value is read directly from HW register RDP, 0x004.
25+
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
29+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
30+
Description: (R) Shows the value held by the ETB status register. The value
31+
is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB RAM Read Pointer register
38+
that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB RAM Write Pointer register
47+
that is used to sets the write pointer to write entries from
48+
the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
50+
51+
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Similar to "trigger_cntr" above except that this value is
56+
read directly from HW register TRG, 0x01C.
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58+
What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the ETB Formatter and Flush Control
78+
register. The value is read directly from HW register FFCR,
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0x304.

‎drivers/hwtracing/coresight/coresight-etb10.c‎

Lines changed: 38 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -579,47 +579,29 @@ static const struct file_operations etb_fops = {
579579
.llseek = no_llseek,
580580
};
581581

582-
static ssize_t status_show(struct device *dev,
583-
struct device_attribute *attr, char *buf)
584-
{
585-
unsigned long flags;
586-
u32 etb_rdr, etb_sr, etb_rrp, etb_rwp;
587-
u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr;
588-
struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
589-
590-
pm_runtime_get_sync(drvdata->dev);
591-
spin_lock_irqsave(&drvdata->spinlock, flags);
592-
CS_UNLOCK(drvdata->base);
593-
594-
etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
595-
etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG);
596-
etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
597-
etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
598-
etb_trg = readl_relaxed(drvdata->base + ETB_TRG);
599-
etb_cr = readl_relaxed(drvdata->base + ETB_CTL_REG);
600-
etb_ffsr = readl_relaxed(drvdata->base + ETB_FFSR);
601-
etb_ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
602-
603-
CS_LOCK(drvdata->base);
604-
spin_unlock_irqrestore(&drvdata->spinlock, flags);
605-
606-
pm_runtime_put(drvdata->dev);
607-
608-
return sprintf(buf,
609-
"Depth:\t\t0x%x\n"
610-
"Status:\t\t0x%x\n"
611-
"RAM read ptr:\t0x%x\n"
612-
"RAM wrt ptr:\t0x%x\n"
613-
"Trigger cnt:\t0x%x\n"
614-
"Control:\t0x%x\n"
615-
"Flush status:\t0x%x\n"
616-
"Flush ctrl:\t0x%x\n",
617-
etb_rdr, etb_sr, etb_rrp, etb_rwp,
618-
etb_trg, etb_cr, etb_ffsr, etb_ffcr);
619-
620-
return -EINVAL;
621-
}
622-
static DEVICE_ATTR_RO(status);
582+
#define coresight_etb10_simple_func(name, offset) \
583+
coresight_simple_func(struct etb_drvdata, name, offset)
584+
585+
coresight_etb10_simple_func(rdp, ETB_RAM_DEPTH_REG);
586+
coresight_etb10_simple_func(sts, ETB_STATUS_REG);
587+
coresight_etb10_simple_func(rrp, ETB_RAM_READ_POINTER);
588+
coresight_etb10_simple_func(rwp, ETB_RAM_WRITE_POINTER);
589+
coresight_etb10_simple_func(trg, ETB_TRG);
590+
coresight_etb10_simple_func(ctl, ETB_CTL_REG);
591+
coresight_etb10_simple_func(ffsr, ETB_FFSR);
592+
coresight_etb10_simple_func(ffcr, ETB_FFCR);
593+
594+
static struct attribute *coresight_etb_mgmt_attrs[] = {
595+
&dev_attr_rdp.attr,
596+
&dev_attr_sts.attr,
597+
&dev_attr_rrp.attr,
598+
&dev_attr_rwp.attr,
599+
&dev_attr_trg.attr,
600+
&dev_attr_ctl.attr,
601+
&dev_attr_ffsr.attr,
602+
&dev_attr_ffcr.attr,
603+
NULL,
604+
};
623605

624606
static ssize_t trigger_cntr_show(struct device *dev,
625607
struct device_attribute *attr, char *buf)
@@ -649,10 +631,23 @@ static DEVICE_ATTR_RW(trigger_cntr);
649631

650632
static struct attribute *coresight_etb_attrs[] = {
651633
&dev_attr_trigger_cntr.attr,
652-
&dev_attr_status.attr,
653634
NULL,
654635
};
655-
ATTRIBUTE_GROUPS(coresight_etb);
636+
637+
static const struct attribute_group coresight_etb_group = {
638+
.attrs = coresight_etb_attrs,
639+
};
640+
641+
static const struct attribute_group coresight_etb_mgmt_group = {
642+
.attrs = coresight_etb_mgmt_attrs,
643+
.name = "mgmt",
644+
};
645+
646+
const struct attribute_group *coresight_etb_groups[] = {
647+
&coresight_etb_group,
648+
&coresight_etb_mgmt_group,
649+
NULL,
650+
};
656651

657652
static int etb_probe(struct amba_device *adev, const struct amba_id *id)
658653
{

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