merge tag release-20171213 of release-4.4 of rockchip-linux/kernel

Change-Id: I34bcf2d53299c47ce1f2dbf68936731fb38f05f8

Author: scorpiochang

Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt

@@ -0,0 +1,67 @@
+* Rockchip PX30 Clock and Reset Unit
+
+The PX30 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
+- compatible: CRU should be "rockchip,px30-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "i2sx_clkin" - external I2S clock - optional,
+ - "gmac_clkin" - external GMAC clock - optional
+
+Example: Clock controller node:
+
+	pmucru: pmu-clock-controller@ff2bc000 {
+		compatible = "rockchip,px30-pmucru";
+		reg = <0x0 0xff2bc000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	cru: clock-controller@ff2b0000 {
+		compatible = "rockchip,px30-cru";
+		reg = <0x0 0xff2b0000 0x0 0x1000>;
+		rockchip,grf = <&grf>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+	uart0: serial@ff030000 {
+		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
+		reg = <0x0 0xff030000 0x0 0x100>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
+		clock-names = "baudclk", "apb_pclk";
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		status = "disabled";
+	};
+

Documentation/devicetree/bindings/leds/leds-is31fl32xx.txt

@@ -0,0 +1,52 @@
+Binding for ISSI IS31FL32xx and Si-En SN32xx LED Drivers
+
+The IS31FL32xx/SN32xx family of LED drivers are I2C devices with multiple
+constant-current channels, each with independent 256-level PWM control.
+Each LED is represented as a sub-node of the device.
+
+Required properties:
+- compatible: one of
+	issi,is31fl3236
+	issi,is31fl3235
+	issi,is31fl3218
+	issi,is31fl3216
+	si-en,sn3218
+	si-en,sn3216
+- reg: I2C slave address
+- address-cells : must be 1
+- size-cells : must be 0
+
+LED sub-node properties:
+- reg : LED channel number (1..N)
+- label :  (optional)
+  see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger :  (optional)
+  see Documentation/devicetree/bindings/leds/common.txt
+
+
+Example:
+
+is31fl3236: led-controller@3c {
+	compatible = "issi,is31fl3236";
+	reg = <0x3c>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	led@1 {
+		reg = <1>;
+		label = "EB:blue:usr0";
+	};
+	led@2 {
+		reg = <2>;
+		label = "EB:blue:usr1";
+	};
+	...
+	led@36 {
+		reg = <36>;
+		label = "EB:blue:usr35";
+	};
+};
+
+For more product information please see the links below:
+http://www.issi.com/US/product-analog-fxled-driver.shtml
+http://www.si-en.com/product.asp?parentid=890

Documentation/devicetree/bindings/mfd/rk816.txt

@@ -25,6 +25,10 @@ Optional properties:
 - vcc5-supply:  The input supply for LDO_REG1, LDO_REG2, LDO_REG3
 - vcc6-supply:  The input supply for LDO_REG4, LDO_REG5, LDO_REG6
 
+- regulator-initial-mode: default mode to set on startup
+- regulator-initial-mode is set as:
+	REGULATOR_MODE_FAST			0x1
+	REGULATOR_MODE_NORMAL			0x2
 Regulators: All the regulators of RK816 to be instantiated shall be
 listed in a child node named 'regulators'. Each regulator is represented
 by a child node of the 'regulators' node.
@@ -104,6 +108,7 @@ Example:
 				regulator-min-microvolt = <750000>;
 				regulator-max-microvolt = <1450000>;
 				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <1>;
 				regulator-state-mem {
 					regulator-off-in-suspend;
 				};
@@ -115,6 +120,7 @@ Example:
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1250000>;
 				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <1>;
 				regulator-state-mem {
 					regulator-on-in-suspend;
 					regulator-suspend-microvolt = <1000000>;
@@ -125,6 +131,7 @@ Example:
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-name = "vcc_ddr";
+				regulator-initial-mode = <1>;
 				regulator-state-mem {
 					regulator-on-in-suspend;
 				};
@@ -136,6 +143,7 @@ Example:
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
 				regulator-name = "vcc33_io";
+				regulator-initial-mode = <1>;
 				regulator-state-mem {
 					regulator-on-in-suspend;
 					regulator-suspend-microvolt = <3300000>;

Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt

@@ -20,6 +20,7 @@ defined as gpio sub-nodes of the pinmux controller.
 
 Required properties for iomux controller:
   - compatible: should be
+		"rockchip,px30-pinctrl":    for Rockchip PX30
 		"rockchip,rk2928-pinctrl":  for Rockchip RK2928
 		"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
 		"rockchip,rk3066b-pinctrl": for Rockchip RK3066b

Documentation/devicetree/bindings/power/rockchip-io-domain.txt

@@ -31,6 +31,8 @@ SoC is on the same page.
 
 Required properties:
 - compatible: should be one of:
+  - "rockchip,px30-io-voltage-domain" for px30
+  - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
   - "rockchip,rk3188-io-voltage-domain" for rk3188
   - "rockchip,rk322x-io-voltage-domain" for rk3228
   - "rockchip,rk3288-io-voltage-domain" for rk3288

Documentation/devicetree/bindings/soc/rockchip/power_domain.txt

@@ -5,6 +5,7 @@ powered up/down by software based on different application scenes to save power.
 
 Required properties for power domain controller:
 - compatible: Should be one of the following.
+	"rockchip,px30-power-controller" - for PX30 SoCs.
 	"rockchip,rk3036-power-controller" - for RK3036 SoCs.
 	"rockchip,rk3128-power-controller" - for RK3128 SoCs.
 	"rockchip,rk3288-power-controller" - for RK3288 SoCs.
@@ -19,6 +20,7 @@ Required properties for power domain controller:
 
 Required properties for power domain sub nodes:
 - reg: index of the power domain, should use macros in:
+	"include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
 	"include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
 	"include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
 	"include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
@@ -97,6 +99,7 @@ Node of a device using power domains must have a power-domains property,
 containing a phandle to the power device node and an index specifying which
 power domain to use.
 The index should use macros in:
+	"include/dt-bindings/power/px30-power.h" - for px30 type power domain.
 	"include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
 	"include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
 	"include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.

arch/arm/boot/dts/Makefile

@@ -528,7 +528,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3229-gva-sdk.dtb \
 	rk3288-evb-act8846.dtb \
 	rk3288-evb-android-act8846-edp.dtb \
+	rk3288-evb-android-rk808-edp.dtb \
 	rk3288-evb-android-rk818-edp.dtb \
+	rk3288-evb-android-rk818-hdmi.dtb \
 	rk3288-evb-android-rk818-lvds.dtb \
 	rk3288-evb-android-rk818-mipi.dtb \
 	rk3288-evb-android-rk818-mipi-edp.dtb \
@@ -543,6 +545,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-miqi.dtb \
 	rk3288-phycore-rdk.dtb \
 	rk3288-popmetal.dtb \
+	rk3288-popmetal-android.dtb \
 	rk3288-r89.dtb \
 	rk3288-rock2-square.dtb \
 	rk3288-veyron-jaq.dtb \

arch/arm/boot/dts/rk3036-kylin.dts

@@ -62,6 +62,8 @@
 		};
 	};
 
+	/delete-node/ psci;
+
 	sdio_pwrseq: sdio-pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		pinctrl-names = "default";

arch/arm/boot/dts/rk3066a-rayeager.dts

@@ -226,6 +226,18 @@
 	cpu0-supply = <&vdd_arm>;
 };
 
+&cpu0_opp_table {
+	opp-816000000 {
+		status = "okay";
+	};
+};
+
+&gpu_opp_table {
+	opp-300000000 {
+		status = "okay";
+	};
+};
+
 &emac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&rmii_rst>;
@@ -366,6 +378,8 @@
 				regulator-name = "vcc25_hdmi";
 				regulator-min-microvolt = <2500000>;
 				regulator-max-microvolt = <2500000>;
+				regulator-always-on;
+				regulator-boot-on;
 			};
 
 			vcca_33: regulator@10 {
@@ -580,6 +594,10 @@
 	status = "okay";
 };
 
+&vop0 {
+	status = "okay";
+};
+
 &wdt {
 	status = "okay";
 };