ASoC: rockchip: i2s: add pcm transfer mode support.

usage: add i2s dts property "rockchip,xfer-mode"

rockchip,xfer-mode = <0>: i2s transfer mode.
rockchip,xfer-mode = <1>: pcm transfer mode.

i2s transfer mode is default.
pcm transfer mode is usually used for bt voice.

Change-Id: Ice04a180c72141d854ffeaa55b8a7b9738597936
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: yi-hsin_hung <yi-hsin_hung@asus.com>

Author: yihsin-hung

sound/soc/rockchip/rockchip_i2s.c

@@ -23,6 +23,9 @@
 
 #include "rockchip_i2s.h"
 
+#define I2S_XFER_MODE	0
+#define PCM_XFER_MODE	1
+
 #define DRV_NAME "rockchip-i2s"
 
 struct rk_i2s_pins {
@@ -50,6 +53,7 @@ struct rk_i2s_dev {
 	bool tx_start;
 	bool rx_start;
 	bool is_master_mode;
+	int xfer_mode; /* 0: i2s, 1: pcm */
 	const struct rk_i2s_pins *pins;
 };
 
@@ -638,6 +642,18 @@ static int rockchip_i2s_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = of_property_read_u32(node, "rockchip,xfer-mode", &i2s->xfer_mode);
+	if (ret < 0)
+		i2s->xfer_mode = I2S_XFER_MODE;
+
+	if (PCM_XFER_MODE == i2s->xfer_mode) {
+		regmap_update_bits(i2s->regmap, I2S_TXCR,
+				   I2S_TXCR_TFS_MASK,
+				   I2S_TXCR_TFS_PCM);
+		regmap_update_bits(i2s->regmap, I2S_RXCR,
+				   I2S_RXCR_TFS_MASK,
+				   I2S_RXCR_TFS_PCM);
+	}
 	return 0;
 
 err_suspend:
@@ -682,6 +698,14 @@ static int rockchip_i2s_resume(struct device *dev)
 	if (ret < 0)
 		return ret;
 	ret = regcache_sync(i2s->regmap);
+	if (PCM_XFER_MODE == i2s->xfer_mode) {
+		regmap_update_bits(i2s->regmap, I2S_TXCR,
+				   I2S_TXCR_TFS_MASK,
+				   I2S_TXCR_TFS_PCM);
+		regmap_update_bits(i2s->regmap, I2S_RXCR,
+				   I2S_RXCR_TFS_MASK,
+				   I2S_RXCR_TFS_PCM);
+	}
 	pm_runtime_put(dev);
 
 	return ret;

sound/soc/rockchip/rockchip_i2s.h

@@ -41,6 +41,7 @@
 #define I2S_TXCR_TFS_SHIFT	5
 #define I2S_TXCR_TFS_I2S	(0 << I2S_TXCR_TFS_SHIFT)
 #define I2S_TXCR_TFS_PCM	(1 << I2S_TXCR_TFS_SHIFT)
+#define I2S_TXCR_TFS_MASK	(1 << I2S_TXCR_TFS_SHIFT)
 #define I2S_TXCR_VDW_SHIFT	0
 #define I2S_TXCR_VDW(x)		((x - 1) << I2S_TXCR_VDW_SHIFT)
 #define I2S_TXCR_VDW_MASK	(0x1f << I2S_TXCR_VDW_SHIFT)
@@ -70,6 +71,7 @@
 #define I2S_RXCR_TFS_SHIFT	5
 #define I2S_RXCR_TFS_I2S	(0 << I2S_RXCR_TFS_SHIFT)
 #define I2S_RXCR_TFS_PCM	(1 << I2S_RXCR_TFS_SHIFT)
+#define I2S_RXCR_TFS_MASK	(1 << I2S_RXCR_TFS_SHIFT)
 #define I2S_RXCR_VDW_SHIFT	0
 #define I2S_RXCR_VDW(x)		((x - 1) << I2S_RXCR_VDW_SHIFT)
 #define I2S_RXCR_VDW_MASK	(0x1f << I2S_RXCR_VDW_SHIFT)