usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c

Author: wuliangfeng

drivers/usb/dwc3/core.c

@@ -727,6 +727,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	if (dwc->tx_ipgap_linecheck_dis_quirk)
 		reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 
+	if (dwc->maximum_speed == USB_SPEED_HIGH ||
+	    dwc->maximum_speed == USB_SPEED_FULL)
+		reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+
 	dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 
 	if (dwc->grxthrcfg[0] > 0) {

drivers/usb/dwc3/core.h

@@ -202,6 +202,7 @@
 
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	(1 << 24)
 
 /* Global USB2 PHY Configuration Register */