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mathieupoiriermathieupoirier
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coresight: tmc: introducing new header file
The amount of #define, enumeration and structure definition is big enough to justify moving them to a new header file. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 4c324b5f0e8a692c8d077da9d18533820c2ab636)
1 parent 00bc807 commit c3e22ca

2 files changed

Lines changed: 123 additions & 101 deletions

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‎drivers/hwtracing/coresight/coresight-tmc.c‎

Lines changed: 1 addition & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -30,107 +30,7 @@
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#include <linux/amba/bus.h>
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#include "coresight-priv.h"
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#define TMC_RSZ 0x004
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#define TMC_STS 0x00c
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#define TMC_RRD 0x010
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#define TMC_RRP 0x014
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#define TMC_RWP 0x018
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#define TMC_TRG 0x01c
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#define TMC_CTL 0x020
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#define TMC_RWD 0x024
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#define TMC_MODE 0x028
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#define TMC_LBUFLEVEL 0x02c
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#define TMC_CBUFLEVEL 0x030
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#define TMC_BUFWM 0x034
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#define TMC_RRPHI 0x038
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#define TMC_RWPHI 0x03c
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#define TMC_AXICTL 0x110
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#define TMC_DBALO 0x118
50-
#define TMC_DBAHI 0x11c
51-
#define TMC_FFSR 0x300
52-
#define TMC_FFCR 0x304
53-
#define TMC_PSCR 0x308
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#define TMC_ITMISCOP0 0xee0
55-
#define TMC_ITTRFLIN 0xee8
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#define TMC_ITATBDATA0 0xeec
57-
#define TMC_ITATBCTR2 0xef0
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#define TMC_ITATBCTR1 0xef4
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#define TMC_ITATBCTR0 0xef8
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/* register description */
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/* TMC_CTL - 0x020 */
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#define TMC_CTL_CAPT_EN BIT(0)
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/* TMC_STS - 0x00C */
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#define TMC_STS_TRIGGERED BIT(1)
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/* TMC_AXICTL - 0x110 */
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#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
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#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
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#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
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#define TMC_AXICTL_WR_BURST_16 0xF00
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/* TMC_FFCR - 0x304 */
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#define TMC_FFCR_EN_FMT BIT(0)
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#define TMC_FFCR_EN_TI BIT(1)
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#define TMC_FFCR_FON_FLIN BIT(4)
75-
#define TMC_FFCR_FON_TRIG_EVT BIT(5)
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#define TMC_FFCR_FLUSHMAN BIT(6)
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#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
78-
#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
79-
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#define TMC_STS_TMCREADY_BIT 2
81-
#define TMC_FFCR_FLUSHMAN_BIT 6
82-
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enum tmc_config_type {
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TMC_CONFIG_TYPE_ETB,
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TMC_CONFIG_TYPE_ETR,
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TMC_CONFIG_TYPE_ETF,
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};
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enum tmc_mode {
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TMC_MODE_CIRCULAR_BUFFER,
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TMC_MODE_SOFTWARE_FIFO,
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TMC_MODE_HARDWARE_FIFO,
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};
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95-
enum tmc_mem_intf_width {
96-
TMC_MEM_INTF_WIDTH_32BITS = 0x2,
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TMC_MEM_INTF_WIDTH_64BITS = 0x3,
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TMC_MEM_INTF_WIDTH_128BITS = 0x4,
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TMC_MEM_INTF_WIDTH_256BITS = 0x5,
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};
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/**
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* struct tmc_drvdata - specifics associated to an TMC component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
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* @spinlock: only one at a time pls.
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* @read_count: manages preparation of buffer for reading.
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* @buf: area of memory where trace data get sent.
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* @paddr: DMA start location in RAM.
112-
* @vaddr: virtual representation of @paddr.
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* @size: @buf size.
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* @enable: this TMC is being used.
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* @config_type: TMC variant, must be of type @tmc_config_type.
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* @trigger_cntr: amount of words to store after a trigger.
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*/
118-
struct tmc_drvdata {
119-
void __iomem *base;
120-
struct device *dev;
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struct coresight_device *csdev;
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struct miscdevice miscdev;
123-
spinlock_t spinlock;
124-
int read_count;
125-
bool reading;
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char *buf;
127-
dma_addr_t paddr;
128-
void *vaddr;
129-
u32 size;
130-
bool enable;
131-
enum tmc_config_type config_type;
132-
u32 trigger_cntr;
133-
};
33+
#include "coresight-tmc.h"
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static void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
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{

‎drivers/hwtracing/coresight/coresight-tmc.h‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _CORESIGHT_TMC_H
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#define _CORESIGHT_TMC_H
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#define TMC_RSZ 0x004
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#define TMC_STS 0x00c
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#define TMC_RRD 0x010
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#define TMC_RRP 0x014
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#define TMC_RWP 0x018
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#define TMC_TRG 0x01c
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#define TMC_CTL 0x020
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#define TMC_RWD 0x024
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#define TMC_MODE 0x028
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#define TMC_LBUFLEVEL 0x02c
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#define TMC_CBUFLEVEL 0x030
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#define TMC_BUFWM 0x034
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#define TMC_RRPHI 0x038
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#define TMC_RWPHI 0x03c
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#define TMC_AXICTL 0x110
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#define TMC_DBALO 0x118
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#define TMC_DBAHI 0x11c
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#define TMC_FFSR 0x300
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#define TMC_FFCR 0x304
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#define TMC_PSCR 0x308
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#define TMC_ITMISCOP0 0xee0
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#define TMC_ITTRFLIN 0xee8
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#define TMC_ITATBDATA0 0xeec
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#define TMC_ITATBCTR2 0xef0
45+
#define TMC_ITATBCTR1 0xef4
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#define TMC_ITATBCTR0 0xef8
47+
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/* register description */
49+
/* TMC_CTL - 0x020 */
50+
#define TMC_CTL_CAPT_EN BIT(0)
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/* TMC_STS - 0x00C */
52+
#define TMC_STS_TRIGGERED BIT(1)
53+
/* TMC_AXICTL - 0x110 */
54+
#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
55+
#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
56+
#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
57+
#define TMC_AXICTL_WR_BURST_16 0xF00
58+
/* TMC_FFCR - 0x304 */
59+
#define TMC_FFCR_EN_FMT BIT(0)
60+
#define TMC_FFCR_EN_TI BIT(1)
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#define TMC_FFCR_FON_FLIN BIT(4)
62+
#define TMC_FFCR_FON_TRIG_EVT BIT(5)
63+
#define TMC_FFCR_FLUSHMAN BIT(6)
64+
#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
65+
#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
66+
67+
#define TMC_STS_TMCREADY_BIT 2
68+
#define TMC_FFCR_FLUSHMAN_BIT 6
69+
70+
enum tmc_config_type {
71+
TMC_CONFIG_TYPE_ETB,
72+
TMC_CONFIG_TYPE_ETR,
73+
TMC_CONFIG_TYPE_ETF,
74+
};
75+
76+
enum tmc_mode {
77+
TMC_MODE_CIRCULAR_BUFFER,
78+
TMC_MODE_SOFTWARE_FIFO,
79+
TMC_MODE_HARDWARE_FIFO,
80+
};
81+
82+
enum tmc_mem_intf_width {
83+
TMC_MEM_INTF_WIDTH_32BITS = 0x2,
84+
TMC_MEM_INTF_WIDTH_64BITS = 0x3,
85+
TMC_MEM_INTF_WIDTH_128BITS = 0x4,
86+
TMC_MEM_INTF_WIDTH_256BITS = 0x5,
87+
};
88+
89+
/**
90+
* struct tmc_drvdata - specifics associated to an TMC component
91+
* @base: memory mapped base address for this component.
92+
* @dev: the device entity associated to this component.
93+
* @csdev: component vitals needed by the framework.
94+
* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
95+
* @spinlock: only one at a time pls.
96+
* @read_count: manages preparation of buffer for reading.
97+
* @buf: area of memory where trace data get sent.
98+
* @paddr: DMA start location in RAM.
99+
* @vaddr: virtual representation of @paddr.
100+
* @size: @buf size.
101+
* @enable: this TMC is being used.
102+
* @config_type: TMC variant, must be of type @tmc_config_type.
103+
* @trigger_cntr: amount of words to store after a trigger.
104+
*/
105+
struct tmc_drvdata {
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void __iomem *base;
107+
struct device *dev;
108+
struct coresight_device *csdev;
109+
struct miscdevice miscdev;
110+
spinlock_t spinlock;
111+
int read_count;
112+
bool reading;
113+
char *buf;
114+
dma_addr_t paddr;
115+
void __iomem *vaddr;
116+
u32 size;
117+
bool enable;
118+
enum tmc_config_type config_type;
119+
u32 trigger_cntr;
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};
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122+
#endif

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