clk: rockchip: rk3288: remove the flag ROCKCHIP_PLL_SYNC_RATE for GPLL

If pwm regulator is enabled in uboot, the rate of pclk_pwm can't be
changed, otherwise the voltage may be abnormal. The gpll is the parent
clock of pclk_pwm, its rate also can't be changed.

Change-Id: I493de867ec6d0f8308a03f5ad6fe2244bbae7d11
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

Author: finley1226

drivers/clk/rockchip/clk-rk3288.c

@@ -211,7 +211,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
 	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
 		     RK3288_MODE_CON, 8, 7, 0, rk3288_pll_rates),
 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
-		     RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
+		     RK3288_MODE_CON, 12, 8, 0, rk3288_pll_rates),
 	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
 		     RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 };