|
112 | 112 | opp-shared; |
113 | 113 |
|
114 | 114 | rockchip,leakage-voltage-sel = < |
115 | | - 1 8 0 |
116 | | - 9 254 1 |
| 115 | + 1 10 0 |
| 116 | + 11 254 1 |
117 | 117 | >; |
118 | 118 | nvmem-cells = <&cpu_leakage>; |
119 | 119 | nvmem-cell-names = "cpu_leakage"; |
120 | 120 |
|
121 | 121 | opp-408000000 { |
122 | 122 | opp-hz = /bits/ 64 <408000000>; |
123 | | - opp-microvolt = <975000 975000 1325000>; |
124 | | - opp-microvolt-L0 = <975000 975000 1325000>; |
125 | | - opp-microvolt-L1 = <950000 950000 1325000>; |
| 123 | + opp-microvolt = <950000 950000 1350000>; |
| 124 | + opp-microvolt-L0 = <950000 950000 1350000>; |
| 125 | + opp-microvolt-L1 = <950000 950000 1350000>; |
126 | 126 | clock-latency-ns = <40000>; |
127 | 127 | opp-suspend; |
128 | 128 | }; |
129 | 129 | opp-600000000 { |
130 | 130 | opp-hz = /bits/ 64 <600000000>; |
131 | | - opp-microvolt = <975000 975000 1325000>; |
132 | | - opp-microvolt-L0 = <975000 975000 1325000>; |
133 | | - opp-microvolt-L1 = <950000 950000 1325000>; |
| 131 | + opp-microvolt = <950000 950000 1350000>; |
| 132 | + opp-microvolt-L0 = <950000 950000 1350000>; |
| 133 | + opp-microvolt-L1 = <950000 950000 1350000>; |
134 | 134 | clock-latency-ns = <40000>; |
135 | 135 | }; |
136 | 136 | opp-816000000 { |
137 | 137 | opp-hz = /bits/ 64 <816000000>; |
138 | | - opp-microvolt = <1025000 1025000 1325000>; |
139 | | - opp-microvolt-L0 = <1025000 1025000 1325000>; |
140 | | - opp-microvolt-L1 = <1000000 1000000 1325000>; |
| 138 | + opp-microvolt = <1050000 1050000 1350000>; |
| 139 | + opp-microvolt-L0 = <1050000 1050000 1350000>; |
| 140 | + opp-microvolt-L1 = <1000000 1000000 1350000>; |
141 | 141 | clock-latency-ns = <40000>; |
142 | 142 | }; |
143 | 143 | opp-1008000000 { |
144 | 144 | opp-hz = /bits/ 64 <1008000000>; |
145 | | - opp-microvolt = <1125000 1125000 1325000>; |
146 | | - opp-microvolt-L0 = <1125000 1125000 1325000>; |
147 | | - opp-microvolt-L1 = <1100000 1100000 1325000>; |
| 145 | + opp-microvolt = <1150000 1150000 1350000>; |
| 146 | + opp-microvolt-L0 = <1150000 1150000 1350000>; |
| 147 | + opp-microvolt-L1 = <1100000 1100000 1350000>; |
148 | 148 | clock-latency-ns = <40000>; |
149 | 149 | }; |
150 | 150 | opp-1200000000 { |
151 | 151 | opp-hz = /bits/ 64 <1200000000>; |
152 | | - opp-microvolt = <1250000 1250000 1325000>; |
153 | | - opp-microvolt-L0 = <1250000 1250000 1325000>; |
154 | | - opp-microvolt-L1 = <1225000 1225000 1325000>; |
| 152 | + opp-microvolt = <1275000 1275000 1350000>; |
| 153 | + opp-microvolt-L0 = <1275000 1275000 1350000>; |
| 154 | + opp-microvolt-L1 = <1225000 1225000 1350000>; |
155 | 155 | clock-latency-ns = <40000>; |
156 | 156 | }; |
157 | 157 | opp-1296000000 { |
158 | 158 | opp-hz = /bits/ 64 <1296000000>; |
159 | | - opp-microvolt = <1325000 1325000 1325000>; |
160 | | - opp-microvolt-L0 = <1325000 1325000 1325000>; |
161 | | - opp-microvolt-L1 = <1300000 1300000 1325000>; |
| 159 | + opp-microvolt = <1350000 1350000 1350000>; |
| 160 | + opp-microvolt-L0 = <1350000 1350000 1350000>; |
| 161 | + opp-microvolt-L1 = <1300000 1300000 1350000>; |
162 | 162 | clock-latency-ns = <40000>; |
163 | 163 | }; |
164 | 164 | }; |
|
699 | 699 | compatible = "operating-points-v2"; |
700 | 700 |
|
701 | 701 | rockchip,leakage-voltage-sel = < |
702 | | - 1 8 0 |
703 | | - 9 254 1 |
| 702 | + 1 10 0 |
| 703 | + 11 254 1 |
704 | 704 | >; |
705 | 705 | nvmem-cells = <&logic_leakage>; |
706 | 706 | nvmem-cell-names = "gpu_leakage"; |
707 | 707 |
|
708 | 708 | opp-200000000 { |
709 | 709 | opp-hz = /bits/ 64 <200000000>; |
710 | | - opp-microvolt = <925000>; |
711 | | - opp-microvolt-L0 = <925000>; |
712 | | - opp-microvolt-L1 = <900000>; |
| 710 | + opp-microvolt = <950000>; |
| 711 | + opp-microvolt-L0 = <950000>; |
| 712 | + opp-microvolt-L1 = <950000>; |
713 | 713 | }; |
714 | 714 | opp-300000000 { |
715 | 715 | opp-hz = /bits/ 64 <300000000>; |
|
725 | 725 | }; |
726 | 726 | opp-500000000 { |
727 | 727 | opp-hz = /bits/ 64 <500000000>; |
728 | | - opp-microvolt = <1125000>; |
729 | | - opp-microvolt-L0 = <1125000>; |
| 728 | + opp-microvolt = <1150000>; |
| 729 | + opp-microvolt-L0 = <1150000>; |
730 | 730 | opp-microvolt-L1 = <1100000>; |
731 | 731 | }; |
732 | 732 | }; |
|
820 | 820 | compatible = "operating-points-v2"; |
821 | 821 |
|
822 | 822 | rockchip,leakage-voltage-sel = < |
823 | | - 1 8 0 |
824 | | - 9 254 1 |
| 823 | + 1 10 0 |
| 824 | + 11 254 1 |
825 | 825 | >; |
826 | 826 | nvmem-cells = <&logic_leakage>; |
827 | 827 | nvmem-cell-names = "rkvdec_leakage"; |
|
1451 | 1451 | compatible = "operating-points-v2"; |
1452 | 1452 |
|
1453 | 1453 | rockchip,leakage-voltage-sel = < |
1454 | | - 1 8 0 |
1455 | | - 9 254 1 |
| 1454 | + 1 10 0 |
| 1455 | + 11 254 1 |
1456 | 1456 | >; |
1457 | 1457 | nvmem-cells = <&logic_leakage>; |
1458 | 1458 | nvmem-cell-names = "ddr_leakage"; |
1459 | 1459 |
|
1460 | 1460 | opp-400000000 { |
1461 | 1461 | opp-hz = /bits/ 64 <400000000>; |
1462 | | - opp-microvolt = <925000>; |
1463 | | - opp-microvolt-L0 = <925000>; |
1464 | | - opp-microvolt-L1 = <900000>; |
| 1462 | + opp-microvolt = <950000>; |
| 1463 | + opp-microvolt-L0 = <950000>; |
| 1464 | + opp-microvolt-L1 = <950000>; |
1465 | 1465 | status = "disabled"; |
1466 | 1466 | }; |
1467 | 1467 | opp-600000000 { |
|
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