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Commit d362c39

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Liang Chen
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arm64: dts: rockchip: adjust opp-table by leakage for rk3328 SoCs
Change-Id: Ic827fe9f868a71e6f7a69f91df43d5f7a23bc5d3 Signed-off-by: Liang Chen <cl@rock-chips.com>
1 parent b72c852 commit d362c39

1 file changed

Lines changed: 34 additions & 34 deletions

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arch/arm64/boot/dts/rockchip/rk3328.dtsi

Lines changed: 34 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -112,53 +112,53 @@
112112
opp-shared;
113113

114114
rockchip,leakage-voltage-sel = <
115-
1 8 0
116-
9 254 1
115+
1 10 0
116+
11 254 1
117117
>;
118118
nvmem-cells = <&cpu_leakage>;
119119
nvmem-cell-names = "cpu_leakage";
120120

121121
opp-408000000 {
122122
opp-hz = /bits/ 64 <408000000>;
123-
opp-microvolt = <975000 975000 1325000>;
124-
opp-microvolt-L0 = <975000 975000 1325000>;
125-
opp-microvolt-L1 = <950000 950000 1325000>;
123+
opp-microvolt = <950000 950000 1350000>;
124+
opp-microvolt-L0 = <950000 950000 1350000>;
125+
opp-microvolt-L1 = <950000 950000 1350000>;
126126
clock-latency-ns = <40000>;
127127
opp-suspend;
128128
};
129129
opp-600000000 {
130130
opp-hz = /bits/ 64 <600000000>;
131-
opp-microvolt = <975000 975000 1325000>;
132-
opp-microvolt-L0 = <975000 975000 1325000>;
133-
opp-microvolt-L1 = <950000 950000 1325000>;
131+
opp-microvolt = <950000 950000 1350000>;
132+
opp-microvolt-L0 = <950000 950000 1350000>;
133+
opp-microvolt-L1 = <950000 950000 1350000>;
134134
clock-latency-ns = <40000>;
135135
};
136136
opp-816000000 {
137137
opp-hz = /bits/ 64 <816000000>;
138-
opp-microvolt = <1025000 1025000 1325000>;
139-
opp-microvolt-L0 = <1025000 1025000 1325000>;
140-
opp-microvolt-L1 = <1000000 1000000 1325000>;
138+
opp-microvolt = <1050000 1050000 1350000>;
139+
opp-microvolt-L0 = <1050000 1050000 1350000>;
140+
opp-microvolt-L1 = <1000000 1000000 1350000>;
141141
clock-latency-ns = <40000>;
142142
};
143143
opp-1008000000 {
144144
opp-hz = /bits/ 64 <1008000000>;
145-
opp-microvolt = <1125000 1125000 1325000>;
146-
opp-microvolt-L0 = <1125000 1125000 1325000>;
147-
opp-microvolt-L1 = <1100000 1100000 1325000>;
145+
opp-microvolt = <1150000 1150000 1350000>;
146+
opp-microvolt-L0 = <1150000 1150000 1350000>;
147+
opp-microvolt-L1 = <1100000 1100000 1350000>;
148148
clock-latency-ns = <40000>;
149149
};
150150
opp-1200000000 {
151151
opp-hz = /bits/ 64 <1200000000>;
152-
opp-microvolt = <1250000 1250000 1325000>;
153-
opp-microvolt-L0 = <1250000 1250000 1325000>;
154-
opp-microvolt-L1 = <1225000 1225000 1325000>;
152+
opp-microvolt = <1275000 1275000 1350000>;
153+
opp-microvolt-L0 = <1275000 1275000 1350000>;
154+
opp-microvolt-L1 = <1225000 1225000 1350000>;
155155
clock-latency-ns = <40000>;
156156
};
157157
opp-1296000000 {
158158
opp-hz = /bits/ 64 <1296000000>;
159-
opp-microvolt = <1325000 1325000 1325000>;
160-
opp-microvolt-L0 = <1325000 1325000 1325000>;
161-
opp-microvolt-L1 = <1300000 1300000 1325000>;
159+
opp-microvolt = <1350000 1350000 1350000>;
160+
opp-microvolt-L0 = <1350000 1350000 1350000>;
161+
opp-microvolt-L1 = <1300000 1300000 1350000>;
162162
clock-latency-ns = <40000>;
163163
};
164164
};
@@ -699,17 +699,17 @@
699699
compatible = "operating-points-v2";
700700

701701
rockchip,leakage-voltage-sel = <
702-
1 8 0
703-
9 254 1
702+
1 10 0
703+
11 254 1
704704
>;
705705
nvmem-cells = <&logic_leakage>;
706706
nvmem-cell-names = "gpu_leakage";
707707

708708
opp-200000000 {
709709
opp-hz = /bits/ 64 <200000000>;
710-
opp-microvolt = <925000>;
711-
opp-microvolt-L0 = <925000>;
712-
opp-microvolt-L1 = <900000>;
710+
opp-microvolt = <950000>;
711+
opp-microvolt-L0 = <950000>;
712+
opp-microvolt-L1 = <950000>;
713713
};
714714
opp-300000000 {
715715
opp-hz = /bits/ 64 <300000000>;
@@ -725,8 +725,8 @@
725725
};
726726
opp-500000000 {
727727
opp-hz = /bits/ 64 <500000000>;
728-
opp-microvolt = <1125000>;
729-
opp-microvolt-L0 = <1125000>;
728+
opp-microvolt = <1150000>;
729+
opp-microvolt-L0 = <1150000>;
730730
opp-microvolt-L1 = <1100000>;
731731
};
732732
};
@@ -820,8 +820,8 @@
820820
compatible = "operating-points-v2";
821821

822822
rockchip,leakage-voltage-sel = <
823-
1 8 0
824-
9 254 1
823+
1 10 0
824+
11 254 1
825825
>;
826826
nvmem-cells = <&logic_leakage>;
827827
nvmem-cell-names = "rkvdec_leakage";
@@ -1451,17 +1451,17 @@
14511451
compatible = "operating-points-v2";
14521452

14531453
rockchip,leakage-voltage-sel = <
1454-
1 8 0
1455-
9 254 1
1454+
1 10 0
1455+
11 254 1
14561456
>;
14571457
nvmem-cells = <&logic_leakage>;
14581458
nvmem-cell-names = "ddr_leakage";
14591459

14601460
opp-400000000 {
14611461
opp-hz = /bits/ 64 <400000000>;
1462-
opp-microvolt = <925000>;
1463-
opp-microvolt-L0 = <925000>;
1464-
opp-microvolt-L1 = <900000>;
1462+
opp-microvolt = <950000>;
1463+
opp-microvolt-L0 = <950000>;
1464+
opp-microvolt-L1 = <950000>;
14651465
status = "disabled";
14661466
};
14671467
opp-600000000 {

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