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coresight: tmc: adding sysFS management entries
Adding management registers that convey implementation specific characteristics. Those are useful for trace configuration and collection along with general trouble shooting. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 7d83d17795efce95def54a13ccd6c3f80de6e8f0)
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Lines changed: 120 additions & 64 deletions

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‎Documentation/ABI/testing/sysfs-bus-coresight-devices-tmc‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,3 +6,80 @@ Description: (RW) Disables write access to the Trace RAM by stopping the
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formatter after a defined number of words have been stored
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following the trigger event. Additional interface for this
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driver are expected to be added as it matures.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Defines the size, in 32-bit words, of the local RAM buffer.
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The value is read directly from HW register RSZ, 0x004.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC status register. The value
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is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC RAM Read Pointer register
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that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC RAM Write Pointer register
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that is used to sets the write pointer to write entries from
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the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Similar to "trigger_cntr" above except that this value is
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read directly from HW register TRG, 0x01C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Formatter and Flush Control
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register. The value is read directly from HW register FFCR,
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0x304.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Shows the value held by the TMC Mode register, which
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indicate the mode the device has been configured to enact. The
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The value is read directly from the MODE register, 0x028.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the capabilities of the Coresight TMC.
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The value is read directly from the DEVID register, 0xFC8,

‎drivers/hwtracing/coresight/coresight-tmc.c‎

Lines changed: 43 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -556,56 +556,38 @@ static const struct file_operations tmc_fops = {
556556
.llseek = no_llseek,
557557
};
558558

559-
static ssize_t status_show(struct device *dev,
560-
struct device_attribute *attr, char *buf)
561-
{
562-
unsigned long flags;
563-
u32 tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg;
564-
u32 tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr;
565-
u32 devid;
566-
struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
567-
568-
pm_runtime_get_sync(drvdata->dev);
569-
spin_lock_irqsave(&drvdata->spinlock, flags);
570-
CS_UNLOCK(drvdata->base);
571-
572-
tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ);
573-
tmc_sts = readl_relaxed(drvdata->base + TMC_STS);
574-
tmc_rrp = readl_relaxed(drvdata->base + TMC_RRP);
575-
tmc_rwp = readl_relaxed(drvdata->base + TMC_RWP);
576-
tmc_trg = readl_relaxed(drvdata->base + TMC_TRG);
577-
tmc_ctl = readl_relaxed(drvdata->base + TMC_CTL);
578-
tmc_ffsr = readl_relaxed(drvdata->base + TMC_FFSR);
579-
tmc_ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
580-
tmc_mode = readl_relaxed(drvdata->base + TMC_MODE);
581-
tmc_pscr = readl_relaxed(drvdata->base + TMC_PSCR);
582-
devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
583-
584-
CS_LOCK(drvdata->base);
585-
spin_unlock_irqrestore(&drvdata->spinlock, flags);
586-
pm_runtime_put(drvdata->dev);
587-
588-
return sprintf(buf,
589-
"Depth:\t\t0x%x\n"
590-
"Status:\t\t0x%x\n"
591-
"RAM read ptr:\t0x%x\n"
592-
"RAM wrt ptr:\t0x%x\n"
593-
"Trigger cnt:\t0x%x\n"
594-
"Control:\t0x%x\n"
595-
"Flush status:\t0x%x\n"
596-
"Flush ctrl:\t0x%x\n"
597-
"Mode:\t\t0x%x\n"
598-
"PSRC:\t\t0x%x\n"
599-
"DEVID:\t\t0x%x\n",
600-
tmc_rsz, tmc_sts, tmc_rrp, tmc_rwp, tmc_trg,
601-
tmc_ctl, tmc_ffsr, tmc_ffcr, tmc_mode, tmc_pscr, devid);
602-
603-
return -EINVAL;
604-
}
605-
static DEVICE_ATTR_RO(status);
559+
#define coresight_tmc_simple_func(name, offset) \
560+
coresight_simple_func(struct tmc_drvdata, name, offset)
561+
562+
coresight_tmc_simple_func(rsz, TMC_RSZ);
563+
coresight_tmc_simple_func(sts, TMC_STS);
564+
coresight_tmc_simple_func(rrp, TMC_RRP);
565+
coresight_tmc_simple_func(rwp, TMC_RWP);
566+
coresight_tmc_simple_func(trg, TMC_TRG);
567+
coresight_tmc_simple_func(ctl, TMC_CTL);
568+
coresight_tmc_simple_func(ffsr, TMC_FFSR);
569+
coresight_tmc_simple_func(ffcr, TMC_FFCR);
570+
coresight_tmc_simple_func(mode, TMC_MODE);
571+
coresight_tmc_simple_func(pscr, TMC_PSCR);
572+
coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
573+
574+
static struct attribute *coresight_tmc_mgmt_attrs[] = {
575+
&dev_attr_rsz.attr,
576+
&dev_attr_sts.attr,
577+
&dev_attr_rrp.attr,
578+
&dev_attr_rwp.attr,
579+
&dev_attr_trg.attr,
580+
&dev_attr_ctl.attr,
581+
&dev_attr_ffsr.attr,
582+
&dev_attr_ffcr.attr,
583+
&dev_attr_mode.attr,
584+
&dev_attr_pscr.attr,
585+
&dev_attr_devid.attr,
586+
NULL,
587+
};
606588

607-
static ssize_t trigger_cntr_show(struct device *dev,
608-
struct device_attribute *attr, char *buf)
589+
ssize_t trigger_cntr_show(struct device *dev,
590+
struct device_attribute *attr, char *buf)
609591
{
610592
struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
611593
unsigned long val = drvdata->trigger_cntr;
@@ -630,26 +612,25 @@ static ssize_t trigger_cntr_store(struct device *dev,
630612
}
631613
static DEVICE_ATTR_RW(trigger_cntr);
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633-
static struct attribute *coresight_etb_attrs[] = {
615+
static struct attribute *coresight_tmc_attrs[] = {
634616
&dev_attr_trigger_cntr.attr,
635-
&dev_attr_status.attr,
636617
NULL,
637618
};
638-
ATTRIBUTE_GROUPS(coresight_etb);
639619

640-
static struct attribute *coresight_etr_attrs[] = {
641-
&dev_attr_trigger_cntr.attr,
642-
&dev_attr_status.attr,
643-
NULL,
620+
static const struct attribute_group coresight_tmc_group = {
621+
.attrs = coresight_tmc_attrs,
644622
};
645-
ATTRIBUTE_GROUPS(coresight_etr);
646623

647-
static struct attribute *coresight_etf_attrs[] = {
648-
&dev_attr_trigger_cntr.attr,
649-
&dev_attr_status.attr,
624+
static const struct attribute_group coresight_tmc_mgmt_group = {
625+
.attrs = coresight_tmc_mgmt_attrs,
626+
.name = "mgmt",
627+
};
628+
629+
const struct attribute_group *coresight_tmc_groups[] = {
630+
&coresight_tmc_group,
631+
&coresight_tmc_mgmt_group,
650632
NULL,
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};
652-
ATTRIBUTE_GROUPS(coresight_etf);
653634

654635
static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
655636
{
@@ -725,20 +706,18 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
725706
desc->pdata = pdata;
726707
desc->dev = dev;
727708
desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
709+
desc->groups = coresight_tmc_groups;
728710

729711
if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
730712
desc->type = CORESIGHT_DEV_TYPE_SINK;
731713
desc->ops = &tmc_etb_cs_ops;
732-
desc->groups = coresight_etb_groups;
733714
} else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
734715
desc->type = CORESIGHT_DEV_TYPE_SINK;
735716
desc->ops = &tmc_etr_cs_ops;
736-
desc->groups = coresight_etr_groups;
737717
} else {
738718
desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
739719
desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
740720
desc->ops = &tmc_etf_cs_ops;
741-
desc->groups = coresight_etf_groups;
742721
}
743722

744723
drvdata->csdev = coresight_register(desc);

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