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bivvyrkhuangtao
bivvy
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rkhuangtao
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drm/rockchip: lvds: Add support for rk3366
Change-Id: Iaf54c4667042b0b24a9083cb7ca931c1b0603804 Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
1 parent 7604d94 commit d86682d

3 files changed

Lines changed: 77 additions & 43 deletions

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Documentation/devicetree/bindings/video/rockchip-lvds.txt renamed to Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,8 @@ Rockchip RK3288 LVDS interface
44
Required properties:
55
- compatible: matching the soc type, one of
66
- "rockchip,rk3288-lvds";
7-
- "rockchip,rk33xx-lvds";
7+
- "rockchip,rk3366-lvds";
8+
- "rockchip,rk3368-lvds";
89

910
- reg: physical base address of the controller and length
1011
of memory mapped region.
@@ -90,7 +91,7 @@ For Rockchip RK3288:
9091
For Rockchip RK3368:
9192

9293
lvds: lvds@ff968000 {
93-
compatible = "rockchip,rk33xx-lvds";
94+
compatible = "rockchip,rk3368-lvds";
9495
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
9596
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
9697
clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
@@ -106,4 +107,4 @@ For Rockchip RK3368:
106107
...
107108

108109
};
109-
};
110+
};

‎drivers/gpu/drm/rockchip/rockchip_lvds.c‎

Lines changed: 56 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,8 @@ struct rockchip_lvds_soc_data {
5454
int grf_soc_con6;
5555
int grf_soc_con7;
5656
int grf_soc_con15;
57+
58+
bool has_vop_sel;
5759
};
5860

5961
struct rockchip_lvds {
@@ -215,7 +217,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds)
215217
return 0;
216218
}
217219

218-
static int rk3368_lvds_poweron(struct rockchip_lvds *lvds)
220+
static int rk336x_lvds_poweron(struct rockchip_lvds *lvds)
219221
{
220222
u32 delay_times = 20;
221223

@@ -255,7 +257,7 @@ static int rk3368_lvds_poweron(struct rockchip_lvds *lvds)
255257
return 0;
256258
}
257259

258-
static void rk3368_output_ttl(struct rockchip_lvds *lvds)
260+
static void rk336x_output_ttl(struct rockchip_lvds *lvds)
259261
{
260262
u32 val = 0;
261263

@@ -270,10 +272,10 @@ static void rk3368_output_ttl(struct rockchip_lvds *lvds)
270272
v_MSB_SEL(1) | v_DIG_INTER_RST(1);
271273
lvds_writel(lvds, MIPIPHY_REGE0, val);
272274

273-
rk3368_lvds_poweron(lvds);
275+
rk336x_lvds_poweron(lvds);
274276
}
275277

276-
static void rk3368_output_lvds(struct rockchip_lvds *lvds)
278+
static void rk336x_output_lvds(struct rockchip_lvds *lvds)
277279
{
278280
/* digital internal disable */
279281
lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(0));
@@ -289,16 +291,16 @@ static void rk3368_output_lvds(struct rockchip_lvds *lvds)
289291
m_MSB_SEL | m_DIG_INTER_RST,
290292
v_MSB_SEL(1) | v_DIG_INTER_RST(1));
291293

292-
rk3368_lvds_poweron(lvds);
294+
rk336x_lvds_poweron(lvds);
293295
lvds_msk_reg(lvds, MIPIPHY_REGE1, m_DIG_INTER_EN, v_DIG_INTER_EN(1));
294296
}
295297

296-
static int rk3368_lvds_output(struct rockchip_lvds *lvds)
298+
static int rk336x_lvds_output(struct rockchip_lvds *lvds)
297299
{
298300
if (lvds->output == DISPLAY_OUTPUT_RGB)
299-
rk3368_output_ttl(lvds);
301+
rk336x_output_ttl(lvds);
300302
else
301-
rk3368_output_lvds(lvds);
303+
rk336x_output_lvds(lvds);
302304
return 0;
303305
}
304306

@@ -328,8 +330,8 @@ static int rockchip_lvds_poweron(struct rockchip_lvds *lvds)
328330
}
329331
if (LVDS_CHIP(lvds) == RK3288_LVDS)
330332
rk3288_lvds_poweron(lvds);
331-
else if (LVDS_CHIP(lvds) == RK3368_LVDS)
332-
rk3368_lvds_output(lvds);
333+
else if (LVDS_CHIP(lvds) == RK336X_LVDS)
334+
rk336x_lvds_output(lvds);
333335

334336
return 0;
335337
}
@@ -353,8 +355,8 @@ static void rockchip_lvds_poweroff(struct rockchip_lvds *lvds)
353355
pm_runtime_put(lvds->dev);
354356
if (lvds->pclk)
355357
clk_disable(lvds->pclk);
356-
} else if (LVDS_CHIP(lvds) == RK3368_LVDS) {
357-
val = v_RK3368_LVDSMODE_EN(0) | v_RK3368_MIPIPHY_TTL_EN(0);
358+
} else if (LVDS_CHIP(lvds) == RK336X_LVDS) {
359+
val = v_RK336X_LVDSMODE_EN(0) | v_RK336X_MIPIPHY_TTL_EN(0);
358360
ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con7, val);
359361
if (ret != 0) {
360362
dev_err(lvds->dev, "Could not write to GRF: %d\n", ret);
@@ -513,7 +515,7 @@ static void rockchip_lvds_encoder_mode_set(struct drm_encoder *encoder,
513515
dev_err(lvds->dev, "Could not write to GRF: %d\n", ret);
514516
return;
515517
}
516-
} else if (LVDS_CHIP(lvds) == RK3368_LVDS) {
518+
} else if (LVDS_CHIP(lvds) == RK336X_LVDS) {
517519
if (lvds->output == DISPLAY_OUTPUT_RGB) {
518520
/* iomux to lcdc */
519521
if (lvds->pins && !IS_ERR(lvds->pins->default_state))
@@ -522,18 +524,18 @@ static void rockchip_lvds_encoder_mode_set(struct drm_encoder *encoder,
522524

523525
lvds_dsi_writel(lvds, 0x0, 0x4);/*set clock lane enable*/
524526
/* enable lvds mode */
525-
val = v_RK3368_LVDSMODE_EN(0) |
526-
v_RK3368_MIPIPHY_TTL_EN(1) |
527-
v_RK3368_MIPIPHY_LANE0_EN(1) |
528-
v_RK3368_MIPIDPI_FORCEX_EN(1);
527+
val = v_RK336X_LVDSMODE_EN(0) |
528+
v_RK336X_MIPIPHY_TTL_EN(1) |
529+
v_RK336X_MIPIPHY_LANE0_EN(1) |
530+
v_RK336X_MIPIDPI_FORCEX_EN(1);
529531
ret = regmap_write(lvds->grf,
530532
lvds->soc_data->grf_soc_con7, val);
531533
if (ret != 0) {
532534
dev_err(lvds->dev,
533535
"Could not write to GRF: %d\n", ret);
534536
return;
535537
}
536-
val = v_RK3368_FORCE_JETAG(0);
538+
val = v_RK336X_FORCE_JETAG(0);
537539
ret = regmap_write(lvds->grf,
538540
lvds->soc_data->grf_soc_con15, val);
539541
if (ret != 0) {
@@ -543,13 +545,14 @@ static void rockchip_lvds_encoder_mode_set(struct drm_encoder *encoder,
543545
}
544546
} else if (lvds->output == DISPLAY_OUTPUT_LVDS) {
545547
/* enable lvds mode */
546-
val = v_RK3368_LVDSMODE_EN(1) | v_RK3368_MIPIPHY_TTL_EN(0);
548+
val = v_RK336X_LVDSMODE_EN(1) |
549+
v_RK336X_MIPIPHY_TTL_EN(0);
547550
/* config lvds_format */
548-
val |= v_RK3368_LVDS_OUTPUT_FORMAT(lvds->format);
551+
val |= v_RK336X_LVDS_OUTPUT_FORMAT(lvds->format);
549552
/* LSB receive mode */
550-
val |= v_RK3368_LVDS_MSBSEL(LVDS_MSB_D7);
551-
val |= v_RK3368_MIPIPHY_LANE0_EN(1) |
552-
v_RK3368_MIPIDPI_FORCEX_EN(1);
553+
val |= v_RK336X_LVDS_MSBSEL(LVDS_MSB_D7);
554+
val |= v_RK336X_MIPIPHY_LANE0_EN(1) |
555+
v_RK336X_MIPIDPI_FORCEX_EN(1);
553556
ret = regmap_write(lvds->grf,
554557
lvds->soc_data->grf_soc_con7, val);
555558
if (ret != 0) {
@@ -567,6 +570,9 @@ static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds,
567570
u32 val;
568571
int ret;
569572

573+
if (!lvds->soc_data->has_vop_sel)
574+
return 0;
575+
570576
ret = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder);
571577
if (ret < 0)
572578
return ret;
@@ -581,7 +587,14 @@ static int rockchip_lvds_set_vop_source(struct rockchip_lvds *lvds,
581587
ret = regmap_write(lvds->grf, lvds->soc_data->grf_soc_con6, val);
582588
if (ret < 0)
583589
return ret;
590+
} else {
591+
if (ret)
592+
val = RK3366_LVDS_VOP_SEL_LIT;
593+
else
594+
val = RK3366_LVDS_VOP_SEL_BIG;
595+
regmap_write(lvds->grf, RK3366_GRF_SOC_CON0, val);
584596
}
597+
585598
return 0;
586599
}
587600

@@ -637,14 +650,21 @@ static struct rockchip_lvds_soc_data rk3288_lvds_data = {
637650
.chip_type = RK3288_LVDS,
638651
.grf_soc_con6 = 0x025c,
639652
.grf_soc_con7 = 0x0260,
653+
.has_vop_sel = true,
654+
};
655+
656+
static struct rockchip_lvds_soc_data rk3366_lvds_data = {
657+
.chip_type = RK336X_LVDS,
658+
.grf_soc_con7 = RK3366_GRF_SOC_CON5,
659+
.grf_soc_con15 = RK3366_GRF_SOC_CON6,
660+
.has_vop_sel = true,
640661
};
641662

642-
static struct rockchip_lvds_soc_data rk33xx_lvds_data = {
643-
.chip_type = RK3368_LVDS,
644-
.grf_soc_con5 = 0x0414,
645-
.grf_soc_con6 = 0x0418,
646-
.grf_soc_con7 = 0x041c,
647-
.grf_soc_con15 = 0x043c,
663+
static struct rockchip_lvds_soc_data rk3368_lvds_data = {
664+
.chip_type = RK336X_LVDS,
665+
.grf_soc_con7 = RK3368_GRF_SOC_CON7,
666+
.grf_soc_con15 = RK3368_GRF_SOC_CON15,
667+
.has_vop_sel = false,
648668
};
649669

650670
static const struct of_device_id rockchip_lvds_dt_ids[] = {
@@ -653,8 +673,12 @@ static const struct of_device_id rockchip_lvds_dt_ids[] = {
653673
.data = &rk3288_lvds_data
654674
},
655675
{
656-
.compatible = "rockchip,rk33xx-lvds",
657-
.data = &rk33xx_lvds_data
676+
.compatible = "rockchip,rk3366-lvds",
677+
.data = &rk3366_lvds_data
678+
},
679+
{
680+
.compatible = "rockchip,rk3368-lvds",
681+
.data = &rk3368_lvds_data
658682
},
659683
{}
660684
};
@@ -830,7 +854,7 @@ static int rockchip_lvds_probe(struct platform_device *pdev)
830854
lvds->regs = devm_ioremap_resource(&pdev->dev, res);
831855
if (IS_ERR(lvds->regs))
832856
return PTR_ERR(lvds->regs);
833-
} else if (LVDS_CHIP(lvds) == RK3368_LVDS) {
857+
} else if (LVDS_CHIP(lvds) == RK336X_LVDS) {
834858
/* lvds regs on MIPIPHY_REG */
835859
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
836860
"mipi_lvds_phy");

‎drivers/gpu/drm/rockchip/rockchip_lvds.h‎

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,15 @@
8989

9090
#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)
9191

92+
#define RK3366_GRF_SOC_CON0 0x0400
93+
#define RK3366_LVDS_VOP_SEL_LIT (BITS_MASK(1, 1, 0) | BITS_EN(1, 0))
94+
#define RK3366_LVDS_VOP_SEL_BIG (BITS_MASK(0, 1, 0) | BITS_EN(1, 0))
95+
#define RK3366_GRF_SOC_CON5 0x0414
96+
#define RK3366_GRF_SOC_CON6 0x0418
97+
98+
#define RK3368_GRF_SOC_CON7 0x041c
99+
#define RK3368_GRF_SOC_CON15 0x043c
100+
92101
#define LVDS_FMT_MASK (0x07 << 16)
93102
#define LVDS_MSB BIT(3)
94103
#define LVDS_DUAL BIT(4)
@@ -169,13 +178,13 @@
169178
#define v_LANE1_EN(x) BITS_MASK(x, 1, 6)
170179
#define v_LANE0_EN(x) BITS_MASK(x, 1, 7)
171180

172-
#define v_RK3368_LVDS_OUTPUT_FORMAT(x) (BITS_MASK(x, 3, 13) | BITS_EN(3, 13))
173-
#define v_RK3368_LVDS_MSBSEL(x) (BITS_MASK(x, 1, 11) | BITS_EN(1, 11))
174-
#define v_RK3368_LVDSMODE_EN(x) (BITS_MASK(x, 1, 12) | BITS_EN(1, 12))
175-
#define v_RK3368_MIPIPHY_TTL_EN(x) (BITS_MASK(x, 1, 15) | BITS_EN(1, 15))
176-
#define v_RK3368_MIPIPHY_LANE0_EN(x) (BITS_MASK(x, 1, 5) | BITS_EN(1, 5))
177-
#define v_RK3368_MIPIDPI_FORCEX_EN(x) (BITS_MASK(x, 1, 6) | BITS_EN(1, 6))
178-
#define v_RK3368_FORCE_JETAG(x) (BITS_MASK(x, 1, 13) | BITS_EN(1, 13))
181+
#define v_RK336X_LVDS_OUTPUT_FORMAT(x) (BITS_MASK(x, 3, 13) | BITS_EN(3, 13))
182+
#define v_RK336X_LVDS_MSBSEL(x) (BITS_MASK(x, 1, 11) | BITS_EN(1, 11))
183+
#define v_RK336X_LVDSMODE_EN(x) (BITS_MASK(x, 1, 12) | BITS_EN(1, 12))
184+
#define v_RK336X_MIPIPHY_TTL_EN(x) (BITS_MASK(x, 1, 15) | BITS_EN(1, 15))
185+
#define v_RK336X_MIPIPHY_LANE0_EN(x) (BITS_MASK(x, 1, 5) | BITS_EN(1, 5))
186+
#define v_RK336X_MIPIDPI_FORCEX_EN(x) (BITS_MASK(x, 1, 6) | BITS_EN(1, 6))
187+
#define v_RK336X_FORCE_JETAG(x) (BITS_MASK(x, 1, 13) | BITS_EN(1, 13))
179188

180189
enum {
181190
LVDS_MSB_D0 = 0,
@@ -184,7 +193,7 @@ enum {
184193

185194
enum rockchip_lvds_sub_devtype {
186195
RK3288_LVDS,
187-
RK3368_LVDS,
196+
RK336X_LVDS,
188197
};
189198

190199
#endif /* _ROCKCHIP_LVDS_ */

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