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clk: rockchip: px30: Fix gpu frequency overflowing
It needs to contains rate and mux clk for gpu composite clk, so that the clk_composite_set_rate_and_parent function can be called. Change-Id: I9818df2adbbcf40f616d2ca230cd83ea1ef2c14f Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
1 parent f09c785 commit dd6270d

1 file changed

Lines changed: 4 additions & 7 deletions

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drivers/clk/rockchip/clk-px30.c

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -338,15 +338,12 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
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PX30_CLKGATE_CON(17), 4, GFLAGS),
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/* PD_GPU */
341-
COMPOSITE_NODIV(0, "clk_gpu_src", mux_4plls_p, 0,
342-
PX30_CLKSEL_CON(1), 6, 2, MFLAGS,
341+
COMPOSITE(0, "clk_gpu_src", mux_4plls_p, 0,
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PX30_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 4, DFLAGS,
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PX30_CLKGATE_CON(0), 8, GFLAGS),
344-
COMPOSITE_NOMUX(0, "clk_gpu_div", "clk_gpu_src", CLK_SET_RATE_PARENT,
345-
PX30_CLKSEL_CON(1), 0, 4, DFLAGS,
346-
PX30_CLKGATE_CON(0), 12, GFLAGS),
347-
GATE(ACLK_GPU, "clk_gpu_pre", "clk_gpu_div", 0,
344+
GATE(ACLK_GPU, "clk_gpu", "clk_gpu_src", 0,
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PX30_CLKGATE_CON(0), 10, GFLAGS),
349-
COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu_pre", CLK_IGNORE_UNUSED,
346+
COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
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PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
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PX30_CLKGATE_CON(17), 10, GFLAGS),
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GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,

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