arm64: dts: rockchip: rk3328: fix vepu clk define error

1.vepu aclk is ACLK_H264 and hclk is HCLK_H264
2.vepu need clk_core clk define
3.add h264&h265 power domain

Change-Id: I419e544cf86d90b2b8d88dd13dfed49d31a24991
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>

Author: buluess

arch/arm64/boot/dts/rockchip/rk3328.dtsi

@@ -723,6 +723,7 @@
 		mode_ctrl = <0x40c>;
 		name = "h265e";
 		allocator = <1>;
+		power-domains = <&power RK3328_PD_HEVC>;
 		status = "disabled";
 	};
 
@@ -742,8 +743,10 @@
 		iommus = <&vepu_mmu>;
 		reg = <0x0 0xff340000 0x0 0x400>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
-		clock-names = "aclk_vcodec", "hclk_vcodec";
+		clocks = <&cru ACLK_H264>, <&cru HCLK_H264>,
+			<&cru SCLK_VENC_CORE>;
+		clock-names = "aclk_vcodec", "hclk_vcodec",
+			"clk_core";
 		resets = <&cru SRST_RKVENC_H264_H>,
 			<&cru SRST_RKVENC_H264_A>;
 		reset-names = "video_h", "video_a";
@@ -752,6 +755,7 @@
 		mode_ctrl = <0x40c>;
 		name = "vepu";
 		allocator = <1>;
+		power-domains = <&power RK3328_PD_HEVC>;
 		status = "disabled";
 	};
 
@@ -760,7 +764,7 @@
 		reg = <0x0 0xff340800 0x0 0x40>;
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "vepu_mmu";
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
 		clock-names = "aclk", "hclk";
 		power-domains = <&power RK3328_PD_HEVC>;
 		#iommu-cells = <0>;