Assign the Serial and Revision vaule of CPU from efuse

Change-Id: Ibfced548e03103912533f95dd0ec9818b8e6be47
Signed-off-by: yi-hsin_hung <yi-hsin_hung@asus.com>

Author: yihsin-hung

drivers/cpufreq/cpufreq-dt.c

@@ -29,6 +29,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/slab.h>
 #include <linux/thermal.h>
+#include <asm/system_info.h>
 
 #define MAX_PROP_NAME_LEN	6
 #define VERSION_ELEMENTS	1
@@ -119,6 +120,9 @@ static int set_opp_info(struct device *dev)
 		chip_vesion = 0;
 		apll_safefreq = SAFE_FREQ;
 	}
+
+	system_rev = (unsigned int)(package_info & 0xf0);
+
 	snprintf(name, MAX_PROP_NAME_LEN, "v%d", chip_vesion);
 	ret = dev_pm_opp_set_prop_name(dev, name);
 	if (ret) {

drivers/nvmem/rockchip-efuse.c

@@ -23,6 +23,8 @@
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <asm/system_info.h>
+#include <linux/crc32.h>
 
 #define EFUSE_A_SHIFT			6
 #define EFUSE_A_MASK			0x3ff
@@ -94,6 +96,64 @@ static const struct of_device_id rockchip_efuse_match[] = {
 };
 MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
 
+static u8 efuse_buf[32] = {};
+static int rockchip_efuse_serial_number(struct rockchip_efuse_chip *efuse, u8 *efuse_buf)
+{
+        u8 *buf = efuse_buf;
+        int ret;
+	size_t bytes = 32;
+	unsigned int offset = 0;
+
+        ret = clk_prepare_enable(efuse->clk);
+        if (ret < 0) {
+                dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
+                return ret;
+        }
+
+        dump_stack();
+
+        writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL);
+        udelay(1);
+        while (bytes--) {
+                writel(readl(efuse->base + REG_EFUSE_CTRL) &
+                             (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
+                             efuse->base + REG_EFUSE_CTRL);
+                writel(readl(efuse->base + REG_EFUSE_CTRL) |
+                             ((offset++ & EFUSE_A_MASK) << EFUSE_A_SHIFT),
+                             efuse->base + REG_EFUSE_CTRL);
+                udelay(1);
+                writel(readl(efuse->base + REG_EFUSE_CTRL) |
+                             EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL);
+                udelay(1);
+                *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
+                writel(readl(efuse->base + REG_EFUSE_CTRL) &
+                     (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL);
+                udelay(1);
+        }
+
+
+        writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL);
+
+        clk_disable_unprepare(efuse->clk);
+
+        return 0;
+}
+
+static void __init rockchip_efuse_set_system_serial(void)
+{
+        int i;
+        u8 buf[16];
+
+        for (i = 0; i < 8; i++) {
+                buf[i] = efuse_buf[8 + (i << 1)];
+                buf[i + 8] = efuse_buf[7 + (i << 1)];
+        }
+
+        system_serial_low = crc32(0, buf, 8);
+        system_serial_high = crc32(system_serial_low, buf + 8, 8);
+}
+
+
 static int __init rockchip_efuse_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -125,6 +185,10 @@ static int __init rockchip_efuse_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, nvmem);
 
+	rockchip_efuse_serial_number(efuse, efuse_buf);
+
+	rockchip_efuse_set_system_serial();
+
 	return 0;
 }