@@ -287,102 +287,64 @@ enum {
287287#define I2S_TDM_RXCR (0x0034)
288288#define I2S_CLKDIV (0x0038)
289289
290- /* PX30 GRF CONFIGS*/
291- #define PX30_I2S0_CLK_IN_SRC_MASK GENMASK(13, 12)
292- #define PX30_I2S0_CLK_IN_SRC_FROM_TX (0x1 << 12)
293- #define PX30_I2S0_CLK_IN_SRC_FROM_RX (0x2 << 12)
294- #define PX30_I2S0_MCLK_OUT_SRC_MSK BIT(5)
295- #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX BIT(5)
296- #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX 0
290+ #define HIWORD_UPDATE (v , h , l ) (((v) << (l)) | (GENMASK((h), (l)) << 16))
297291
298- #define PX30_I2S0_CLK_MSK \
299- (PX30_I2S0_MCLK_OUT_SRC_MSK | \
300- PX30_I2S0_CLK_IN_SRC_MASK)
292+ /* PX30 GRF CONFIGS*/
293+ #define PX30_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 13, 12)
294+ #define PX30_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 13, 12)
295+ #define PX30_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5)
296+ #define PX30_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5)
301297
302298#define PX30_I2S0_CLK_TXONLY \
303- (PX30_I2S0_MCLK_OUT_SRC_FROM_TX | \
304- PX30_I2S0_CLK_IN_SRC_FROM_TX | \
305- (PX30_I2S0_CLK_MSK << 16))
299+ (PX30_I2S0_MCLK_OUT_SRC_FROM_TX | PX30_I2S0_CLK_IN_SRC_FROM_TX)
306300
307301#define PX30_I2S0_CLK_RXONLY \
308- (PX30_I2S0_MCLK_OUT_SRC_FROM_RX | \
309- PX30_I2S0_CLK_IN_SRC_FROM_RX | \
310- (PX30_I2S0_CLK_MSK << 16))
302+ (PX30_I2S0_MCLK_OUT_SRC_FROM_RX | PX30_I2S0_CLK_IN_SRC_FROM_RX)
311303
312304/* RK1808 GRF CONFIGS*/
313- #define RK1808_I2S0_MCLK_OUT_SRC_MSK BIT(2)
314- #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX BIT(2)
315- #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX 0
316- #define RK1808_I2S0_CLK_IN_SRC_MASK GENMASK(1, 0)
317- #define RK1808_I2S0_CLK_IN_SRC_FROM_TX (0x1 << 0)
318- #define RK1808_I2S0_CLK_IN_SRC_FROM_RX (0x2 << 0)
319-
320- #define RK1808_I2S0_CLK_MSK \
321- (RK1808_I2S0_MCLK_OUT_SRC_MSK | \
322- RK1808_I2S0_CLK_IN_SRC_MASK)
305+ #define RK1808_I2S0_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
306+ #define RK1808_I2S0_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
307+ #define RK1808_I2S0_CLK_IN_SRC_FROM_TX HIWORD_UPDATE(1, 1, 0)
308+ #define RK1808_I2S0_CLK_IN_SRC_FROM_RX HIWORD_UPDATE(2, 1, 0)
323309
324310#define RK1808_I2S0_CLK_TXONLY \
325- (RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | \
326- RK1808_I2S0_CLK_IN_SRC_FROM_TX | \
327- (RK1808_I2S0_CLK_MSK << 16))
311+ (RK1808_I2S0_MCLK_OUT_SRC_FROM_TX | RK1808_I2S0_CLK_IN_SRC_FROM_TX)
328312
329313#define RK1808_I2S0_CLK_RXONLY \
330- (RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | \
331- RK1808_I2S0_CLK_IN_SRC_FROM_RX | \
332- (RK1808_I2S0_CLK_MSK << 16))
314+ (RK1808_I2S0_MCLK_OUT_SRC_FROM_RX | RK1808_I2S0_CLK_IN_SRC_FROM_RX)
333315
334316/* RK3308 GRF CONFIGS*/
335- #define RK3308_I2S0_8CH_MCLK_OUT_SRC_MSK BIT(10)
336- #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX BIT(10)
337- #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX 0
338- #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_MSK BIT(9)
339- #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX BIT(9)
340- #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX 0
341- #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_MSK BIT(8)
342- #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX BIT(8)
343- #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX 0
344- #define RK3308_I2S1_8CH_MCLK_OUT_SRC_MSK BIT(2)
345- #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX BIT(2)
346- #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX 0
347- #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_MSK BIT(1)
348- #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX BIT(1)
349- #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX 0
350- #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_MSK BIT(0)
351- #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX BIT(0)
352- #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX 0
353-
354- #define RK3308_I2S0_CLK_MSK \
355- (RK3308_I2S0_8CH_MCLK_OUT_SRC_MSK | \
356- RK3308_I2S0_8CH_CLK_IN_RX_SRC_MSK | \
357- RK3308_I2S0_8CH_CLK_IN_TX_SRC_MSK)
317+ #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 10, 10)
318+ #define RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 10, 10)
319+ #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 9, 9)
320+ #define RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 9, 9)
321+ #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 8, 8)
322+ #define RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 8, 8)
323+ #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(1, 2, 2)
324+ #define RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(0, 2, 2)
325+ #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX HIWORD_UPDATE(1, 1, 1)
326+ #define RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX HIWORD_UPDATE(0, 1, 1)
327+ #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX HIWORD_UPDATE(1, 0, 0)
328+ #define RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX HIWORD_UPDATE(0, 0, 0)
358329
359330#define RK3308_I2S0_CLK_TXONLY \
360331 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_TX | \
361332 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_TX | \
362- RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX | \
363- (RK3308_I2S0_CLK_MSK << 16))
333+ RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_TX)
364334
365335#define RK3308_I2S0_CLK_RXONLY \
366336 (RK3308_I2S0_8CH_MCLK_OUT_SRC_FROM_RX | \
367337 RK3308_I2S0_8CH_CLK_IN_RX_SRC_FROM_RX | \
368- RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX | \
369- (RK3308_I2S0_CLK_MSK << 16))
370-
371- #define RK3308_I2S1_CLK_MSK \
372- (RK3308_I2S1_8CH_MCLK_OUT_SRC_MSK | \
373- RK3308_I2S1_8CH_CLK_IN_RX_SRC_MSK | \
374- RK3308_I2S1_8CH_CLK_IN_TX_SRC_MSK)
338+ RK3308_I2S0_8CH_CLK_IN_TX_SRC_FROM_RX)
375339
376340#define RK3308_I2S1_CLK_TXONLY \
377341 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_TX | \
378342 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_TX | \
379- RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX | \
380- (RK3308_I2S1_CLK_MSK << 16))
343+ RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_TX)
381344
382345#define RK3308_I2S1_CLK_RXONLY \
383346 (RK3308_I2S1_8CH_MCLK_OUT_SRC_FROM_RX | \
384347 RK3308_I2S1_8CH_CLK_IN_RX_SRC_FROM_RX | \
385- RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX | \
386- (RK3308_I2S1_CLK_MSK << 16))
348+ RK3308_I2S1_8CH_CLK_IN_TX_SRC_FROM_RX)
387349
388350#endif /* _ROCKCHIP_I2S_TDM_H */
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