Skip to content

Commit f65bf33

Browse files
Marc ZyngierAlex Shi
Marc Zyngier
authored and
Alex Shi
committed
arm64: KVM: Turn system register numbers to an enum
Having the system register numbers as #defines has been a pain since day one, as the ordering is pretty fragile, and moving things around leads to renumbering and epic conflict resolutions. Now that we're mostly acessing the sysreg file in C, an enum is a much better type to use, and we can clean things up a bit. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> (cherry picked from commit 9d8415d6c148a16b6d906a96f0596851d7e4d607) Signed-off-by: Alex Shi <alex.shi@linaro.org>
1 parent 493f9d8 commit f65bf33

12 files changed

Lines changed: 87 additions & 82 deletions

File tree

‎arch/arm64/include/asm/kvm_asm.h‎

Lines changed: 0 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -20,82 +20,6 @@
2020

2121
#include <asm/virt.h>
2222

23-
/*
24-
* 0 is reserved as an invalid value.
25-
* Order *must* be kept in sync with the hyp switch code.
26-
*/
27-
#define MPIDR_EL1 1 /* MultiProcessor Affinity Register */
28-
#define CSSELR_EL1 2 /* Cache Size Selection Register */
29-
#define SCTLR_EL1 3 /* System Control Register */
30-
#define ACTLR_EL1 4 /* Auxiliary Control Register */
31-
#define CPACR_EL1 5 /* Coprocessor Access Control */
32-
#define TTBR0_EL1 6 /* Translation Table Base Register 0 */
33-
#define TTBR1_EL1 7 /* Translation Table Base Register 1 */
34-
#define TCR_EL1 8 /* Translation Control Register */
35-
#define ESR_EL1 9 /* Exception Syndrome Register */
36-
#define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */
37-
#define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */
38-
#define FAR_EL1 12 /* Fault Address Register */
39-
#define MAIR_EL1 13 /* Memory Attribute Indirection Register */
40-
#define VBAR_EL1 14 /* Vector Base Address Register */
41-
#define CONTEXTIDR_EL1 15 /* Context ID Register */
42-
#define TPIDR_EL0 16 /* Thread ID, User R/W */
43-
#define TPIDRRO_EL0 17 /* Thread ID, User R/O */
44-
#define TPIDR_EL1 18 /* Thread ID, Privileged */
45-
#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
46-
#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
47-
#define PAR_EL1 21 /* Physical Address Register */
48-
#define MDSCR_EL1 22 /* Monitor Debug System Control Register */
49-
#define MDCCINT_EL1 23 /* Monitor Debug Comms Channel Interrupt Enable Reg */
50-
51-
/* 32bit specific registers. Keep them at the end of the range */
52-
#define DACR32_EL2 24 /* Domain Access Control Register */
53-
#define IFSR32_EL2 25 /* Instruction Fault Status Register */
54-
#define FPEXC32_EL2 26 /* Floating-Point Exception Control Register */
55-
#define DBGVCR32_EL2 27 /* Debug Vector Catch Register */
56-
#define NR_SYS_REGS 28
57-
58-
/* 32bit mapping */
59-
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
60-
#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
61-
#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
62-
#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
63-
#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
64-
#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
65-
#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
66-
#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
67-
#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
68-
#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
69-
#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
70-
#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
71-
#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
72-
#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
73-
#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
74-
#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
75-
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
76-
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
77-
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
78-
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
79-
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
80-
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
81-
#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
82-
#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
83-
#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
84-
#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
85-
#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
86-
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
87-
#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
88-
89-
#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
90-
#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
91-
#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
92-
#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
93-
#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
94-
#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
95-
#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
96-
97-
#define NR_COPRO_REGS (NR_SYS_REGS * 2)
98-
9923
#define ARM_EXCEPTION_IRQ 0
10024
#define ARM_EXCEPTION_TRAP 1
10125

‎arch/arm64/include/asm/kvm_emulate.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@
2626

2727
#include <asm/esr.h>
2828
#include <asm/kvm_arm.h>
29-
#include <asm/kvm_asm.h>
3029
#include <asm/kvm_mmio.h>
3130
#include <asm/ptrace.h>
3231
#include <asm/cputype.h>

‎arch/arm64/include/asm/kvm_host.h‎

Lines changed: 80 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@
2525
#include <linux/types.h>
2626
#include <linux/kvm_types.h>
2727
#include <asm/kvm.h>
28-
#include <asm/kvm_asm.h>
2928
#include <asm/kvm_mmio.h>
3029

3130
#define __KVM_HAVE_ARCH_INTC_INITIALIZED
@@ -85,6 +84,86 @@ struct kvm_vcpu_fault_info {
8584
u64 hpfar_el2; /* Hyp IPA Fault Address Register */
8685
};
8786

87+
/*
88+
* 0 is reserved as an invalid value.
89+
* Order should be kept in sync with the save/restore code.
90+
*/
91+
enum vcpu_sysreg {
92+
__INVALID_SYSREG__,
93+
MPIDR_EL1, /* MultiProcessor Affinity Register */
94+
CSSELR_EL1, /* Cache Size Selection Register */
95+
SCTLR_EL1, /* System Control Register */
96+
ACTLR_EL1, /* Auxiliary Control Register */
97+
CPACR_EL1, /* Coprocessor Access Control */
98+
TTBR0_EL1, /* Translation Table Base Register 0 */
99+
TTBR1_EL1, /* Translation Table Base Register 1 */
100+
TCR_EL1, /* Translation Control Register */
101+
ESR_EL1, /* Exception Syndrome Register */
102+
AFSR0_EL1, /* Auxilary Fault Status Register 0 */
103+
AFSR1_EL1, /* Auxilary Fault Status Register 1 */
104+
FAR_EL1, /* Fault Address Register */
105+
MAIR_EL1, /* Memory Attribute Indirection Register */
106+
VBAR_EL1, /* Vector Base Address Register */
107+
CONTEXTIDR_EL1, /* Context ID Register */
108+
TPIDR_EL0, /* Thread ID, User R/W */
109+
TPIDRRO_EL0, /* Thread ID, User R/O */
110+
TPIDR_EL1, /* Thread ID, Privileged */
111+
AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
112+
CNTKCTL_EL1, /* Timer Control Register (EL1) */
113+
PAR_EL1, /* Physical Address Register */
114+
MDSCR_EL1, /* Monitor Debug System Control Register */
115+
MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
116+
117+
/* 32bit specific registers. Keep them at the end of the range */
118+
DACR32_EL2, /* Domain Access Control Register */
119+
IFSR32_EL2, /* Instruction Fault Status Register */
120+
FPEXC32_EL2, /* Floating-Point Exception Control Register */
121+
DBGVCR32_EL2, /* Debug Vector Catch Register */
122+
123+
NR_SYS_REGS /* Nothing after this line! */
124+
};
125+
126+
/* 32bit mapping */
127+
#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
128+
#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
129+
#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
130+
#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
131+
#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
132+
#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
133+
#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
134+
#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
135+
#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
136+
#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
137+
#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
138+
#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
139+
#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
140+
#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
141+
#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
142+
#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
143+
#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
144+
#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
145+
#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
146+
#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
147+
#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
148+
#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
149+
#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
150+
#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
151+
#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
152+
#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
153+
#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
154+
#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
155+
#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
156+
157+
#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
158+
#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
159+
#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
160+
#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
161+
#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
162+
#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
163+
#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
164+
165+
#define NR_COPRO_REGS (NR_SYS_REGS * 2)
166+
88167
struct kvm_cpu_context {
89168
struct kvm_regs gp_regs;
90169
union {

‎arch/arm64/include/asm/kvm_mmio.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@
1919
#define __ARM64_KVM_MMIO_H__
2020

2121
#include <linux/kvm_host.h>
22-
#include <asm/kvm_asm.h>
2322
#include <asm/kvm_arm.h>
2423

2524
/*

‎arch/arm64/kernel/asm-offsets.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ int main(void)
125125
DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1));
126126
DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr));
127127
DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs));
128+
DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2]));
128129
DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2));
129130
DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2));
130131
DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));

‎arch/arm64/kvm/guest.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,6 @@
2828
#include <asm/cputype.h>
2929
#include <asm/uaccess.h>
3030
#include <asm/kvm.h>
31-
#include <asm/kvm_asm.h>
3231
#include <asm/kvm_emulate.h>
3332
#include <asm/kvm_coproc.h>
3433

‎arch/arm64/kvm/handle_exit.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#include <linux/kvm_host.h>
2424

2525
#include <asm/esr.h>
26+
#include <asm/kvm_asm.h>
2627
#include <asm/kvm_coproc.h>
2728
#include <asm/kvm_emulate.h>
2829
#include <asm/kvm_mmu.h>

‎arch/arm64/kvm/hyp/debug-sr.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include <linux/compiler.h>
1919
#include <linux/kvm_host.h>
2020

21+
#include <asm/kvm_asm.h>
2122
#include <asm/kvm_mmu.h>
2223

2324
#include "hyp.h"

‎arch/arm64/kvm/hyp/entry.S‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@
2727

2828
#define CPU_GP_REG_OFFSET(x) (CPU_GP_REGS + x)
2929
#define CPU_XREG_OFFSET(x) CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
30-
#define CPU_SYSREG_OFFSET(x) (CPU_SYSREGS + 8*x)
3130

3231
.text
3332
.pushsection .hyp.text, "ax"
@@ -150,7 +149,7 @@ ENTRY(__fpsimd_guest_restore)
150149
// Skip restoring fpexc32 for AArch64 guests
151150
mrs x1, hcr_el2
152151
tbnz x1, #HCR_RW_SHIFT, 1f
153-
ldr x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
152+
ldr x4, [x3, #VCPU_FPEXC32_EL2]
154153
msr fpexc32_el2, x4
155154
1:
156155
ldp x4, lr, [sp], #16

‎arch/arm64/kvm/hyp/sysreg-sr.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include <linux/compiler.h>
1919
#include <linux/kvm_host.h>
2020

21+
#include <asm/kvm_asm.h>
2122
#include <asm/kvm_mmu.h>
2223

2324
#include "hyp.h"

0 commit comments

Comments
 (0)