CHROMIUM: usb: dwc3: rockchip: reset host controller at resume

If we power off the SoC LOGIC rail in S3, it seems that the host
controller comes back in an undefined state, such that the Type C PHY
can't initialize correctly. We need to toggle the USB3-OTG reset before
trying to initialize the PHY, or else it often times out.

Note that the TRM suggests we should be asserting this reset for the
duration of the PHY initialization, but we're still skeptical about
that, and we haven't yet found a case where this seems to have mattered.
Besides, this approach is much easier.

The dwc3 core is going to reinitialize the controller at suspend/resume
anyway (including a "soft reset"), so it should be safe to do this,
regardless of whether the system actually powered off the USB logic.

For hygiene's sake, it's good to wait some small bit of time in between
asserting/de-asserting this reset. Might as well apply this to both
instances of this reset.

BUG=b:62644399
TEST=suspend/resume scarlet with LOGIC disabled in S3; USB comes back OK
     also test suspend/resume on kevin for USB regressions

Change-Id: I5b5354d0fb9c7ed9d2c9044ddfbb5f7709884fb7
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/877404
Reviewed-by: Douglas Anderson <dianders@chromium.org>

Author: wuliangfeng

drivers/usb/dwc3/dwc3-rockchip.c

@@ -945,6 +945,10 @@ static int dwc3_rockchip_resume(struct device *dev)
 	struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 	struct dwc3 *dwc = rockchip->dwc;
 
+	reset_control_assert(rockchip->otg_rst);
+	udelay(1);
+	reset_control_deassert(rockchip->otg_rst);
+
 	rockchip->suspended = false;
 
 	if (rockchip->edev)