Skip to content

Commit feff85e

Browse files
Pratik Patelmathieupoirier
Pratik Patel
authored and
mathieupoirier
committed
coresight: stm: adding driver for CoreSight STM component
This driver adds support for the STM CoreSight IP block, allowing any system compoment (HW or SW) to log and aggregate messages via a single entity. The CoreSight STM exposes an application defined number of channels called stimulus port. Configuration is done using entries in sysfs and channels made available to userspace via configfs. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Michael Williams <michael.williams@arm.com> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit 237483aa5cf43105d148d3f03b29eed47c3e6cf9)
1 parent 27e5d1a commit feff85e

7 files changed

Lines changed: 1047 additions & 2 deletions

File tree

‎Documentation/ABI/testing/sysfs-bus-coresight-devices-stm‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
2+
Date: April 2016
3+
KernelVersion: 4.7
4+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
5+
Description: (RW) Enable/disable tracing on this specific trace macrocell.
6+
Enabling the trace macrocell implies it has been configured
7+
properly and a sink has been identified for it. The path
8+
of coresight components linking the source to the sink is
9+
configured and managed automatically by the coresight framework.
10+
11+
What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
12+
Date: April 2016
13+
KernelVersion: 4.7
14+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
15+
Description: (RW) Provides access to the HW event enable register, used in
16+
conjunction with HW event bank select register.
17+
18+
What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
19+
Date: April 2016
20+
KernelVersion: 4.7
21+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
22+
Description: (RW) Gives access to the HW event block select register
23+
(STMHEBSR) in order to configure up to 256 channels. Used in
24+
conjunction with "hwevent_enable" register as described above.
25+
26+
What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
27+
Date: April 2016
28+
KernelVersion: 4.7
29+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
30+
Description: (RW) Provides access to the stimulus port enable register
31+
(STMSPER). Used in conjunction with "port_select" described
32+
below.
33+
34+
What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
35+
Date: April 2016
36+
KernelVersion: 4.7
37+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
38+
Description: (RW) Used to determine which bank of stimulus port bit in
39+
register STMSPER (see above) apply to.
40+
41+
What: /sys/bus/coresight/devices/<memory_map>.stm/status
42+
Date: April 2016
43+
KernelVersion: 4.7
44+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
45+
Description: (R) List various control and status registers. The specific
46+
layout and content is driver specific.
47+
48+
What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
49+
Date: April 2016
50+
KernelVersion: 4.7
51+
Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
52+
Description: (RW) Holds the trace ID that will appear in the trace stream
53+
coming from this trace entity.

‎Documentation/trace/coresight.txt‎

Lines changed: 35 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,8 @@ expected to be accessed and controlled using those entries.
190190
Last but not least, "struct module *owner" is expected to be set to reflect
191191
the information carried in "THIS_MODULE".
192192

193-
How to use
194-
----------
193+
How to use the tracer modules
194+
-----------------------------
195195

196196
Before trace collection can start, a coresight sink needs to be identify.
197197
There is no limit on the amount of sinks (nor sources) that can be enabled at
@@ -297,3 +297,36 @@ Info Tracing enabled
297297
Instruction 13570831 0x8026B584 E28DD00C false ADD sp,sp,#0xc
298298
Instruction 0 0x8026B588 E8BD8000 true LDM sp!,{pc}
299299
Timestamp Timestamp: 17107041535
300+
301+
How to use the STM module
302+
-------------------------
303+
304+
Using the System Trace Macrocell module is the same as the tracers - the only
305+
difference is that clients are driving the trace capture rather
306+
than the program flow through the code.
307+
308+
As with any other CoreSight component, specifics about the STM tracer can be
309+
found in sysfs with more information on each entry being found in [1]:
310+
311+
root@genericarmv8:~# ls /sys/bus/coresight/devices/20100000.stm
312+
enable_source hwevent_select port_enable subsystem uevent
313+
hwevent_enable mgmt port_select traceid
314+
root@genericarmv8:~#
315+
316+
Like any other source a sink needs to be identified and the STM enabled before
317+
being used:
318+
319+
root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20010000.etf/enable_sink
320+
root@genericarmv8:~# echo 1 > /sys/bus/coresight/devices/20100000.stm/enable_source
321+
322+
From there user space applications can request and use channels using the devfs
323+
interface provided for that purpose by the generic STM API:
324+
325+
root@genericarmv8:~# ls -l /dev/20100000.stm
326+
crw------- 1 root root 10, 61 Jan 3 18:11 /dev/20100000.stm
327+
root@genericarmv8:~#
328+
329+
Details on how to use the generic STM API can be found here [2].
330+
331+
[1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-stm
332+
[2]. Documentation/trace/stm.txt

‎drivers/hwtracing/coresight/Kconfig‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,4 +78,15 @@ config CORESIGHT_QCOM_REPLICATOR
7878
programmable ATB replicator sends the ATB trace stream from the
7979
ETB/ETF to the TPIUi and ETR.
8080

81+
config CORESIGHT_STM
82+
bool "CoreSight System Trace Macrocell driver"
83+
depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
84+
select CORESIGHT_LINKS_AND_SINKS
85+
select STM
86+
help
87+
This driver provides support for hardware assisted software
88+
instrumentation based tracing. This is primarily used for
89+
logging useful software events or data coming from various entities
90+
in the system, possibly running different OSs
91+
8192
endif

‎drivers/hwtracing/coresight/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \
1313
obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
1414
coresight-etm4x-sysfs.o
1515
obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
16+
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o

0 commit comments

Comments
 (0)