canio: Add support to teensy 4.1 board

Author: SamantazFox

ports/mimxrt10xx/Makefile

@@ -120,6 +120,7 @@ SRC_SDK := \
 	drivers/snvs_hp/fsl_snvs_hp.c \
 	drivers/snvs_lp/fsl_snvs_lp.c \
 	drivers/trng/fsl_trng.c \
+	drivers/flexcan/fsl_flexcan.c \
 
 ifeq ($(CIRCUITPY_ANALOGIO), 1)
 SRC_SDK +=	drivers/adc_12b1msps_sar/fsl_adc.c \

ports/mimxrt10xx/boards/teensy41/mpconfigboard.mk

@@ -7,5 +7,6 @@ CHIP_VARIANT = MIMXRT1062DVJ6A
 CHIP_FAMILY = MIMXRT1062
 FLASH = W25Q64JV
 CIRCUITPY__EVE = 1
+CIRCUITPY_CANIO = 1
 CIRCUITPY_USB_HOST = 1
 CIRCUITPY_SETTABLE_PROCESSOR_FREQUENCY = 1

ports/mimxrt10xx/boards/teensy41/pins.c

@@ -179,5 +179,23 @@ static const mp_rom_map_elem_t board_module_globals_table[] = {
     {MP_OBJ_NEW_QSTR(MP_QSTR_TX7), MP_ROM_PTR(&pin_GPIO_EMC_31)},
     {MP_OBJ_NEW_QSTR(MP_QSTR_RX8), MP_ROM_PTR(&pin_GPIO_B1_13)},
     {MP_OBJ_NEW_QSTR(MP_QSTR_TX8), MP_ROM_PTR(&pin_GPIO_B1_12)},
+
+    // CAN and CAN-FD
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN1_RX),  MP_ROM_PTR(&pin_GPIO_AD_B1_09)},
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN1_TX),  MP_ROM_PTR(&pin_GPIO_AD_B1_08)},
+
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN2_RX),  MP_ROM_PTR(&pin_GPIO_AD_B0_03)},
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN2_TX),  MP_ROM_PTR(&pin_GPIO_AD_B0_02)},
+
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN3_RX),  MP_ROM_PTR(&pin_GPIO_EMC_37)},
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN3_TX),  MP_ROM_PTR(&pin_GPIO_EMC_36)},
+
+    // "CAN" is an alias for CAN1
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX),  MP_ROM_PTR(&pin_GPIO_AD_B1_09)},
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX),  MP_ROM_PTR(&pin_GPIO_AD_B1_08)},
+
+    // "CANFD" is an alias for CAN3
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CANFD_RX),  MP_ROM_PTR(&pin_GPIO_EMC_37)},
+    {MP_OBJ_NEW_QSTR(MP_QSTR_CANFD_TX),  MP_ROM_PTR(&pin_GPIO_EMC_36)},
 };
 MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/clocks.c

@@ -167,9 +167,9 @@ void clocks_init(void) {
     CLOCK_DisableClock(kCLOCK_Can2S);
     CLOCK_DisableClock(kCLOCK_Can3S);
     /* Set CAN_CLK_PODF. */
-    CLOCK_SetDiv(kCLOCK_CanDiv, 1);
+    CLOCK_SetDiv(kCLOCK_CanDiv, 2); // Clock divider for master flexcan clock source
     /* Set Can clock source. */
-    CLOCK_SetMux(kCLOCK_CanMux, 2);
+    CLOCK_SetMux(kCLOCK_CanMux, 0); // Select 60M clock divided by USB1 PLL (480 MHz) as master flexcan clock source
     /* Disable UART clock gate. */
     CLOCK_DisableClock(kCLOCK_Lpuart1);
     CLOCK_DisableClock(kCLOCK_Lpuart2);

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.c

@@ -276,6 +276,40 @@ const mcu_periph_obj_t mcu_mqs_right_list[3] = {
     PERIPH_PIN(3, 2, 0, 0, &pin_GPIO_B0_00),
 };
 
+CAN_Type *const mcu_can_banks[3] = { CAN1, CAN2, CAN3 };
+
+const mcu_periph_obj_t mcu_can_rx_list[11] = {
+    PERIPH_PIN(1, 4, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT, 0, &pin_GPIO_SD_B1_03),
+    PERIPH_PIN(1, 3, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT, 1, &pin_GPIO_EMC_18),
+    PERIPH_PIN(1, 2, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT, 2, &pin_GPIO_AD_B1_09),
+    PERIPH_PIN(1, 2, kIOMUXC_FLEXCAN1_RX_SELECT_INPUT, 3, &pin_GPIO_B0_03),
+
+    PERIPH_PIN(2, 3, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT, 0, &pin_GPIO_EMC_10),
+    PERIPH_PIN(2, 0, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT, 1, &pin_GPIO_AD_B0_03),
+    PERIPH_PIN(2, 6, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT, 2, &pin_GPIO_AD_B0_15),
+    PERIPH_PIN(2, 6, kIOMUXC_FLEXCAN2_RX_SELECT_INPUT, 3, &pin_GPIO_B1_09),
+
+    PERIPH_PIN(3, 9, 0, 0, &pin_GPIO_EMC_37),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_AD_B0_11),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_AD_B0_15),
+};
+
+const mcu_periph_obj_t mcu_can_tx_list[11] = {
+    PERIPH_PIN(1, 3, 0, 0, &pin_GPIO_EMC_17),
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_AD_B1_08),
+    PERIPH_PIN(1, 2, 0, 0, &pin_GPIO_B0_02),
+    PERIPH_PIN(1, 4, 0, 0, &pin_GPIO_SD_B1_02),
+
+    PERIPH_PIN(2, 3, 0, 0, &pin_GPIO_EMC_09),
+    PERIPH_PIN(2, 0, 0, 0, &pin_GPIO_AD_B0_02),
+    PERIPH_PIN(2, 6, 0, 0, &pin_GPIO_AD_B0_14),
+    PERIPH_PIN(2, 6, 0, 0, &pin_GPIO_B1_08),
+
+    PERIPH_PIN(3, 9, 0, 0, &pin_GPIO_EMC_36),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_AD_B0_10),
+    PERIPH_PIN(3, 8, 0, 0, &pin_GPIO_AD_B0_14),
+};
+
 const mcu_pwm_obj_t mcu_pwm_list[67] = {
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00, &pin_GPIO_EMC_23),
     PWM_PIN(PWM1, kPWM_Module_0, kPWM_PwmA, IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00, &pin_GPIO_SD_B0_00),

ports/mimxrt10xx/peripherals/mimxrt10xx/MIMXRT1062/periph.h

@@ -41,4 +41,8 @@ extern const mcu_periph_obj_t mcu_i2s_mclk_list[7];
 extern const mcu_periph_obj_t mcu_mqs_left_list[3];
 extern const mcu_periph_obj_t mcu_mqs_right_list[3];
 
+extern CAN_Type *const mcu_can_banks[3];
+extern const mcu_periph_obj_t mcu_can_rx_list[11];
+extern const mcu_periph_obj_t mcu_can_tx_list[11];
+
 extern const mcu_pwm_obj_t mcu_pwm_list[67];

ports/mimxrt10xx/tools/gen_peripherals_data.py

@@ -1,4 +1,5 @@
 import sys
+import re
 import pathlib
 import xml.etree.ElementTree as ET
 
@@ -8,6 +9,7 @@
     "LPUART": ["RX", "TX", "RTS", "CTS"],
     "I2S": ["RX_DATA0", "RX_SYNC", "TX_BCLK", "TX_DATA0", "TX_SYNC", "MCLK"],
     "MQS": ["LEFT", "RIGHT"],
+    "CAN": ["RX", "TX"],
 }
 
 SIGNAL_RENAME = {
@@ -21,6 +23,22 @@
     "RX_DATA": "RX_DATA0",
 }
 
+INSTANCE_RENAME = {
+    "FLEXCAN" : "CAN"
+}
+
+INSTANCE_RE = re.compile("([a-zA-Z0-9]+?)([0-9]+)$")
+def rename_instance(instance:str)-> str:
+    instance_match = INSTANCE_RE.match(instance)
+    if instance_match is None:
+        return instance
+    instance_res = instance_match.groups()
+    if len(instance_res) < 2:
+        return instance
+    instance_name = str(instance_res[0])
+    instance_id = str(instance_res[1])
+    return INSTANCE_RENAME.get(instance_name, instance_name) + instance_id
+
 SKIP_LPSR = True
 
 svd_folder = pathlib.Path(sys.argv[1])
@@ -54,6 +72,7 @@
     print(device)
     autogen_warning = autogen_warning_template.format(device)
     svd_fn = svd_folder / device / (device + ".xml")
+
     if not svd_fn.exists():
         svd_fn = svd_folder / device / (device + "_cm7.xml")
 
@@ -144,8 +163,10 @@
         if name.endswith("SELECT_INPUT"):
             name_split = name.split("_")
             instance = name_split[0]
+            instance = rename_instance(instance)
             signal = "_".join(name_split[1:-2])
             signal = SIGNAL_RENAME.get(signal, signal)
+
             if instance not in peripheral_inputs:
                 peripheral_inputs[instance] = {}
             if signal not in peripheral_inputs[instance]:
@@ -161,6 +182,7 @@
                     continue
                 alt = int(alt[3:])
                 value = int(evalue.find("value").text, 0)
+                #print(f"instance: {instance}, signal: {signal}, pin_name: {pin_name}")
                 peripheral_inputs[instance][signal][pin_name] = [alt, name, value]
         # Mux registers come before PAD registers.
         elif name.startswith("SW_MUX_CTL_PAD_GPIO"):
@@ -232,6 +254,7 @@
                         print("skipping", pin_name, connection)
                         continue
                     instance, signal = connection.split("_", maxsplit=1)
+                    instance = rename_instance(instance)
                     signal = SIGNAL_RENAME.get(signal, signal)
                     if instance not in peripheral_inputs:
                         peripheral_inputs[instance] = {}
@@ -288,6 +311,7 @@
         short_name = ptype.lower()
         if short_name.startswith("lp"):
             short_name = short_name[2:]
+
         # Only one MQS exists and it is related to SAI3
         if ptype != "MQS":
             periph_h.append(
@@ -301,6 +325,7 @@
         for signal in SIGNALS[ptype]:
             pin_count = 0
             for instance in instances:
+                ###print(f"instance: {instance}")
                 if instance not in peripheral_inputs or signal not in peripheral_inputs[instance]:
                     continue
                 pin_count += len(peripheral_inputs[instance][signal])