@@ -48,28 +48,22 @@ int metal_sys_init(const struct metal_init_params *params) {
4848 hwsem_reset (METAL_HSEM_REMOTE );
4949 #endif
5050
51- // Enable the hardware semaphore IRQ.
52- NVIC_ClearPendingIRQ (METAL_HSEM_IRQn );
53- NVIC_SetPriority (METAL_HSEM_IRQn , IRQ_PRI_HWSEM );
54- NVIC_EnableIRQ (METAL_HSEM_IRQn );
55-
5651 // If cache management is not enabled, configure the MPU to disable
5752 // caching for the entire Open-AMP shared memory region.
5853 #ifndef VIRTIO_USE_DCACHE
5954 ARM_MPU_Disable ();
60- // NOTE: The startup code uses the first 4 attributes.
61- #define MEMATTR_IDX_NORMAL_NON_CACHEABLE 4
62- ARM_MPU_SetMemAttr (MEMATTR_IDX_NORMAL_NON_CACHEABLE , ARM_MPU_ATTR (
63- ARM_MPU_ATTR_NON_CACHEABLE ,
64- ARM_MPU_ATTR_NON_CACHEABLE ));
6555 MPU -> RNR = METAL_MPU_REGION_ID ;
66- MPU -> RBAR = ARM_MPU_RBAR (METAL_MPU_REGION_BASE , ARM_MPU_SH_NON , 0 , 1 , 0 ); // RO-0, NP-1, XN-0
67- MPU -> RLAR = ARM_MPU_RLAR (METAL_MPU_REGION_BASE + METAL_MPU_REGION_SIZE - 1 , MEMATTR_IDX_NORMAL_NON_CACHEABLE );
56+ MPU -> RBAR = ARM_MPU_RBAR (METAL_MPU_REGION_BASE , ARM_MPU_SH_NON , 0 , 1 , 1 ); // RO-0, NP-1, XN-1
57+ MPU -> RLAR = ARM_MPU_RLAR (METAL_MPU_REGION_BASE + METAL_MPU_REGION_SIZE - 1 , MP_MPU_ATTR_NORMAL_NON_CACHEABLE );
6858 ARM_MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk );
6959 #endif
7060
7161 metal_bus_register (& metal_generic_bus );
7262
63+ // Enable the hardware semaphore IRQ.
64+ NVIC_ClearPendingIRQ (METAL_HSEM_IRQn );
65+ NVIC_SetPriority (METAL_HSEM_IRQn , IRQ_PRI_HWSEM );
66+ NVIC_EnableIRQ (METAL_HSEM_IRQn );
7367 return 0 ;
7468}
7569
0 commit comments