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30 | 30 |
|
31 | 31 | #include "shared-bindings/watchdog/__init__.h" |
32 | 32 | #include "shared-bindings/watchdog/WatchDogTimer.h" |
| 33 | +#include "shared-bindings/microcontroller/__init__.h" |
| 34 | + |
33 | 35 | #include "common-hal/watchdog/WatchDogTimer.h" |
34 | 36 |
|
35 | 37 | #include "component/wdt.h" |
36 | 38 |
|
| 39 | +#define SYNC_CTRL_WRITE while (WDT->SYNCBUSY.reg) {} |
| 40 | + |
| 41 | +static void watchdog_disable(void) { |
| 42 | + // disable watchdog |
| 43 | + WDT->CTRLA.reg = 0; |
| 44 | + SYNC_CTRL_WRITE |
| 45 | +} |
| 46 | + |
| 47 | +static void watchdog_enable(watchdog_watchdogtimer_obj_t *self) { |
| 48 | + // disable watchdog for config |
| 49 | + watchdog_disable(); |
| 50 | + |
| 51 | + int wdt_cycles = (int)(self->timeout * 1024); |
| 52 | + if (wdt_cycles < 8) { |
| 53 | + wdt_cycles = 8; |
| 54 | + } |
| 55 | + |
| 56 | + // ceil(log2(n)) = 32 - __builtin_clz(n - 1) when n > 1 (if int is 32 bits) |
| 57 | + int log2_wdt_cycles = (sizeof(int) * CHAR_BIT) - __builtin_clz(wdt_cycles - 1); |
| 58 | + int setting = log2_wdt_cycles - 3; // CYC8_Val is 0 |
| 59 | + |
| 60 | + OSC32KCTRL->OSCULP32K.bit.EN1K = 1; // Enable out 1K (for WDT) |
| 61 | + |
| 62 | + WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt |
| 63 | + WDT->CONFIG.bit.PER = setting; // Set period for chip reset |
| 64 | + WDT->CTRLA.bit.WEN = 0; // Disable window mode |
| 65 | + SYNC_CTRL_WRITE |
| 66 | + common_hal_watchdog_feed(self); // Clear watchdog interval |
| 67 | + WDT->CTRLA.bit.ENABLE = 1; // Start watchdog now! |
| 68 | + SYNC_CTRL_WRITE |
| 69 | +} |
| 70 | + |
37 | 71 | void common_hal_watchdog_feed(watchdog_watchdogtimer_obj_t *self) { |
38 | 72 | WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY; |
39 | 73 | } |
40 | 74 |
|
41 | 75 | void common_hal_watchdog_deinit(watchdog_watchdogtimer_obj_t *self) { |
42 | | - if (self->mode == WATCHDOGMODE_RESET) { |
43 | | - mp_raise_RuntimeError(translate("WatchDogTimer cannot be deinitialized once mode is set to RESET")); |
44 | | - } else { |
45 | | - self->mode = WATCHDOGMODE_NONE; |
| 76 | + if (self->mode == WATCHDOGMODE_NONE) { |
| 77 | + return; |
46 | 78 | } |
| 79 | + watchdog_disable(); |
| 80 | + self->mode = WATCHDOGMODE_NONE; |
47 | 81 | } |
48 | 82 |
|
49 | 83 | mp_float_t common_hal_watchdog_get_timeout(watchdog_watchdogtimer_obj_t *self) { |
50 | 84 | return self->timeout; |
51 | 85 | } |
52 | 86 |
|
53 | | -STATIC void setup_wdt(watchdog_watchdogtimer_obj_t *self, int setting) { |
54 | | - OSC32KCTRL->OSCULP32K.bit.EN1K = 1; // Enable out 1K (for WDT) |
55 | | - |
56 | | - // disable watchdog for config |
57 | | - WDT->CTRLA.reg = 0; |
58 | | - while (WDT->SYNCBUSY.reg) { // Sync CTRL write |
59 | | - } |
60 | | - |
61 | | - WDT->INTENCLR.reg = WDT_INTENCLR_EW; // Disable early warning interrupt |
62 | | - WDT->CONFIG.bit.PER = setting; // Set period for chip reset |
63 | | - WDT->CTRLA.bit.WEN = 0; // Disable window mode |
64 | | - while (WDT->SYNCBUSY.reg) { // Sync CTRL write |
65 | | - } |
66 | | - common_hal_watchdog_feed(self); // Clear watchdog interval |
67 | | - WDT->CTRLA.bit.ENABLE = 1; // Start watchdog now! |
68 | | - while (WDT->SYNCBUSY.reg) { |
69 | | - } |
70 | | -} |
71 | | - |
72 | 87 | void common_hal_watchdog_set_timeout(watchdog_watchdogtimer_obj_t *self, mp_float_t new_timeout) { |
73 | | - int wdt_cycles = (int)(new_timeout * 1024); |
74 | | - if (wdt_cycles < 8) { |
75 | | - wdt_cycles = 8; |
76 | | - } |
77 | | - if (wdt_cycles > 16384) { |
78 | | - mp_raise_ValueError(translate("timeout duration exceeded the maximum supported value")); |
| 88 | + if (!(self->timeout < new_timeout || self->timeout > new_timeout)) { |
| 89 | + return; |
79 | 90 | } |
80 | | - // ceil(log2(n)) = 32 - __builtin_clz(n - 1) when n > 1 (if int is 32 bits) |
81 | | - int log2_wdt_cycles = (sizeof(int) * CHAR_BIT) - __builtin_clz(wdt_cycles - 1); |
82 | | - int setting = log2_wdt_cycles - 3; // CYC8_Val is 0 |
83 | | - float timeout = (8 << setting) / 1024.f; |
| 91 | + |
| 92 | + mp_arg_validate_int_max(new_timeout, 16, MP_QSTR_timeout); |
| 93 | + self->timeout = new_timeout; |
84 | 94 |
|
85 | 95 | if (self->mode == WATCHDOGMODE_RESET) { |
86 | | - setup_wdt(self, setting); |
| 96 | + watchdog_enable(self); |
87 | 97 | } |
88 | | - self->timeout = timeout; |
89 | 98 | } |
90 | 99 |
|
91 | 100 | watchdog_watchdogmode_t common_hal_watchdog_get_mode(watchdog_watchdogtimer_obj_t *self) { |
92 | 101 | return self->mode; |
93 | 102 | } |
94 | 103 |
|
95 | 104 | void common_hal_watchdog_set_mode(watchdog_watchdogtimer_obj_t *self, watchdog_watchdogmode_t new_mode) { |
96 | | - if (self->mode != new_mode) { |
97 | | - if (new_mode == WATCHDOGMODE_RAISE) { |
98 | | - mp_raise_NotImplementedError(translate("RAISE mode is not implemented")); |
99 | | - } else if (new_mode == WATCHDOGMODE_NONE) { |
| 105 | + if (self->mode == new_mode) { |
| 106 | + return; |
| 107 | + } |
| 108 | + |
| 109 | + switch (new_mode) { |
| 110 | + case WATCHDOGMODE_NONE: |
100 | 111 | common_hal_watchdog_deinit(self); |
101 | | - } |
102 | | - self->mode = new_mode; |
103 | | - common_hal_watchdog_set_timeout(self, self->timeout); |
| 112 | + break; |
| 113 | + case WATCHDOGMODE_RAISE: |
| 114 | + mp_raise_NotImplementedError(NULL); |
| 115 | + break; |
| 116 | + case WATCHDOGMODE_RESET: |
| 117 | + watchdog_enable(self); |
| 118 | + break; |
| 119 | + default: |
| 120 | + return; |
104 | 121 | } |
| 122 | + |
| 123 | + self->mode = new_mode; |
105 | 124 | } |
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