@@ -426,7 +426,7 @@ void ra_i2c_init(R_IIC0_Type *i2c_inst, uint32_t scl, uint32_t sda, uint32_t bau
426426 i2c_inst -> ICCR1_b .ICE = 1 ; // I2C enable
427427 ra_i2c_set_baudrate (i2c_inst , baudrate );
428428 i2c_inst -> ICSER = 0x00 ; // I2C reset bus status enable register
429- i2c_inst -> ICMR3_b .ACKWP = 0x01 ; // I2C allow to write ACKBT (transfer acknowledge bit)
429+ i2c_inst -> ICMR3_b .ACKWP = 0x00 ; // I2C not allow to write ACKBT (transfer acknowledge bit)
430430 i2c_inst -> ICIER = 0xFF ; // Enable all interrupts
431431 i2c_inst -> ICCR1_b .IICRST = 0 ; // I2C internal reset
432432 ra_i2c_irq_enable (i2c_inst );
@@ -480,6 +480,7 @@ void ra_i2c_xunit_read_byte(R_IIC0_Type *i2c_inst, xaction_unit_t *unit) {
480480void ra_i2c_xunit_init (xaction_unit_t * unit , uint8_t * buf , uint32_t size , bool fread , void * next ) {
481481 unit -> m_bytes_transferred = 0 ;
482482 unit -> m_bytes_transfer = size ;
483+ unit -> m_bytes_total = size ;
483484 unit -> m_fread = fread ;
484485 unit -> buf = buf ;
485486 unit -> next = (void * )next ;
@@ -531,6 +532,37 @@ static void ra_i2c_iceri_isr(R_IIC0_Type *i2c_inst) {
531532static void ra_i2c_icrxi_isr (R_IIC0_Type * i2c_inst ) {
532533 xaction_unit_t * unit = current_xaction_unit ;
533534 xaction_t * action = current_xaction ;
535+ // 1 byte or 2 bytes
536+ if (unit -> m_bytes_total <= 2 ) {
537+ if (action -> m_status == RA_I2C_STATUS_AddrWriteCompleted ) {
538+ action -> m_status = RA_I2C_STATUS_FirstReceiveCompleted ;
539+ i2c_inst -> ICMR3_b .WAIT = 1 ;
540+ // need dummy read processes for 1 byte and 2 bytes receive
541+ if (unit -> m_bytes_total == 2 ) {
542+ (void )i2c_inst -> ICDRR ; // dummy read for 2 bytes receive
543+ } else { // m_bytes_total == 1
544+ i2c_inst -> ICMR3_b .ACKWP = 0x01 ; // enable write ACKBT (transfer acknowledge bit)
545+ i2c_inst -> ICMR3_b .ACKBT = 1 ;
546+ i2c_inst -> ICMR3_b .ACKWP = 0x00 ; // disable write ACKBT (transfer acknowledge bit)
547+ (void )i2c_inst -> ICDRR ; // dummy read for 1 byte receive
548+ }
549+ return ;
550+ }
551+ if (unit -> m_bytes_transfer == 2 ) { // last two data
552+ i2c_inst -> ICMR3_b .ACKWP = 0x01 ; // enable write ACKBT (transfer acknowledge bit)
553+ i2c_inst -> ICMR3_b .ACKBT = 1 ;
554+ i2c_inst -> ICMR3_b .ACKWP = 0x00 ; // disable write ACKBT (transfer acknowledge bit)
555+ ra_i2c_xunit_read_byte (i2c_inst , unit );
556+ } else { // last data
557+ action -> m_status = RA_I2C_STATUS_LastReceiveCompleted ;
558+ if (action -> m_stop == true) {
559+ i2c_inst -> ICCR2_b .SP = 1 ; // request top condition
560+ }
561+ ra_i2c_xunit_read_byte (i2c_inst , unit );
562+ }
563+ return ;
564+ }
565+ // 3 bytes or more
534566 if (action -> m_status == RA_I2C_STATUS_AddrWriteCompleted ) {
535567 (void )i2c_inst -> ICDRR ; // dummy read
536568 action -> m_status = RA_I2C_STATUS_FirstReceiveCompleted ;
@@ -542,7 +574,9 @@ static void ra_i2c_icrxi_isr(R_IIC0_Type *i2c_inst) {
542574 }
543575 ra_i2c_xunit_read_byte (i2c_inst , unit );
544576 } else if (unit -> m_bytes_transfer == 2 ) {
577+ i2c_inst -> ICMR3_b .ACKWP = 0x01 ; // enable write ACKBT (transfer acknowledge bit)
545578 i2c_inst -> ICMR3_b .ACKBT = 1 ;
579+ i2c_inst -> ICMR3_b .ACKWP = 0x00 ; // disable write ACKBT (transfer acknowledge bit)
546580 ra_i2c_xunit_read_byte (i2c_inst , unit );
547581 } else {
548582 // last data
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