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James Marsh
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Add all SIMD operations into wasm_interp_fast switch
1 parent f7f1491 commit 5b2ab61

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‎core/iwasm/interpreter/wasm_interp_fast.c‎

Lines changed: 348 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5652,6 +5652,25 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
56525652
GET_OPCODE();
56535653

56545654
switch (opcode) {
5655+
/* Memory */
5656+
case SIMD_v128_load:
5657+
case SIMD_v128_load8x8_s:
5658+
case SIMD_v128_load8x8_u:
5659+
case SIMD_v128_load16x4_s:
5660+
case SIMD_v128_load16x4_u:
5661+
case SIMD_v128_load32x2_s:
5662+
case SIMD_v128_load32x2_u:
5663+
case SIMD_v128_load8_splat:
5664+
case SIMD_v128_load16_splat:
5665+
case SIMD_v128_load32_splat:
5666+
case SIMD_v128_load64_splat:
5667+
case SIMD_v128_store:
5668+
{
5669+
wasm_set_exception(module, "unsupported SIMD opcode");
5670+
break;
5671+
}
5672+
5673+
/* Basic */
56555674
case SIMD_v128_const:
56565675
{
56575676
uint8 *orig_ip = frame_ip;
@@ -5662,6 +5681,128 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
56625681
PUT_V128_TO_ADDR(frame_lp + addr_ret, *(V128 *)orig_ip);
56635682
break;
56645683
}
5684+
case SIMD_v8x16_shuffle:
5685+
case SIMD_v8x16_swizzle:
5686+
{
5687+
wasm_set_exception(module, "unsupported SIMD opcode");
5688+
break;
5689+
}
5690+
5691+
/* Splat */
5692+
case SIMD_i8x16_splat:
5693+
case SIMD_i16x8_splat:
5694+
case SIMD_i32x4_splat:
5695+
case SIMD_i64x2_splat:
5696+
case SIMD_f32x4_splat:
5697+
case SIMD_f64x2_splat:
5698+
{
5699+
wasm_set_exception(module, "unsupported SIMD opcode");
5700+
break;
5701+
}
5702+
5703+
/* Lane */
5704+
case SIMD_i8x16_extract_lane_s:
5705+
case SIMD_i8x16_extract_lane_u:
5706+
case SIMD_i8x16_replace_lane:
5707+
case SIMD_i16x8_extract_lane_s:
5708+
case SIMD_i16x8_extract_lane_u:
5709+
case SIMD_i16x8_replace_lane:
5710+
case SIMD_i32x4_extract_lane:
5711+
case SIMD_i32x4_replace_lane:
5712+
case SIMD_i64x2_extract_lane:
5713+
case SIMD_i64x2_replace_lane:
5714+
case SIMD_f32x4_extract_lane:
5715+
case SIMD_f32x4_replace_lane:
5716+
case SIMD_f64x2_extract_lane:
5717+
case SIMD_f64x2_replace_lane:
5718+
{
5719+
wasm_set_exception(module, "unsupported SIMD opcode");
5720+
break;
5721+
}
5722+
5723+
/* i8x16 comparison operations */
5724+
case SIMD_i8x16_eq:
5725+
case SIMD_i8x16_ne:
5726+
case SIMD_i8x16_lt_s:
5727+
case SIMD_i8x16_lt_u:
5728+
case SIMD_i8x16_gt_s:
5729+
case SIMD_i8x16_gt_u:
5730+
case SIMD_i8x16_le_s:
5731+
case SIMD_i8x16_le_u:
5732+
case SIMD_i8x16_ge_s:
5733+
case SIMD_i8x16_ge_u:
5734+
{
5735+
wasm_set_exception(module, "unsupported SIMD opcode");
5736+
break;
5737+
}
5738+
5739+
/* i16x8 comparison operations */
5740+
case SIMD_i16x8_eq:
5741+
case SIMD_i16x8_ne:
5742+
case SIMD_i16x8_lt_s:
5743+
case SIMD_i16x8_lt_u:
5744+
case SIMD_i16x8_gt_s:
5745+
case SIMD_i16x8_gt_u:
5746+
case SIMD_i16x8_le_s:
5747+
case SIMD_i16x8_le_u:
5748+
case SIMD_i16x8_ge_s:
5749+
case SIMD_i16x8_ge_u:
5750+
{
5751+
wasm_set_exception(module, "unsupported SIMD opcode");
5752+
break;
5753+
}
5754+
5755+
/* i32x4 comparison operations */
5756+
case SIMD_i32x4_eq:
5757+
case SIMD_i32x4_ne:
5758+
case SIMD_i32x4_lt_s:
5759+
case SIMD_i32x4_lt_u:
5760+
case SIMD_i32x4_gt_s:
5761+
case SIMD_i32x4_gt_u:
5762+
case SIMD_i32x4_le_s:
5763+
case SIMD_i32x4_le_u:
5764+
case SIMD_i32x4_ge_s:
5765+
case SIMD_i32x4_ge_u:
5766+
{
5767+
wasm_set_exception(module, "unsupported SIMD opcode");
5768+
break;
5769+
}
5770+
5771+
/* f32x4 comparison operations */
5772+
case SIMD_f32x4_eq:
5773+
case SIMD_f32x4_ne:
5774+
case SIMD_f32x4_lt:
5775+
case SIMD_f32x4_gt:
5776+
case SIMD_f32x4_le:
5777+
case SIMD_f32x4_ge:
5778+
{
5779+
wasm_set_exception(module, "unsupported SIMD opcode");
5780+
break;
5781+
}
5782+
5783+
/* f64x2 comparison operations */
5784+
case SIMD_f64x2_eq:
5785+
case SIMD_f64x2_ne:
5786+
case SIMD_f64x2_lt:
5787+
case SIMD_f64x2_gt:
5788+
case SIMD_f64x2_le:
5789+
case SIMD_f64x2_ge:
5790+
{
5791+
wasm_set_exception(module, "unsupported SIMD opcode");
5792+
break;
5793+
}
5794+
5795+
/* v128 comparison operations */
5796+
case SIMD_v128_not:
5797+
case SIMD_v128_and:
5798+
case SIMD_v128_andnot:
5799+
case SIMD_v128_or:
5800+
case SIMD_v128_xor:
5801+
case SIMD_v128_bitselect:
5802+
{
5803+
wasm_set_exception(module, "unsupported SIMD opcode");
5804+
break;
5805+
}
56655806
case SIMD_v128_any_true:
56665807
{
56675808
V128 value = POP_V128();
@@ -5670,6 +5811,213 @@ wasm_interp_call_func_bytecode(WASMModuleInstance *module,
56705811
value.i64x2[0] != 0 || value.i64x2[1] != 0;
56715812
break;
56725813
}
5814+
5815+
/* load lane operations */
5816+
case SIMD_v128_load8_lane:
5817+
case SIMD_v128_load16_lane:
5818+
case SIMD_v128_load32_lane:
5819+
case SIMD_v128_load64_lane:
5820+
case SIMD_v128_store8_lane:
5821+
case SIMD_v128_store16_lane:
5822+
case SIMD_v128_store32_lane:
5823+
case SIMD_v128_store64_lane:
5824+
case SIMD_v128_load32_zero:
5825+
case SIMD_v128_load64_zero:
5826+
{
5827+
wasm_set_exception(module, "unsupported SIMD opcode");
5828+
break;
5829+
}
5830+
5831+
/* Float conversion */
5832+
case SIMD_f32x4_demote_f64x2_zero:
5833+
case SIMD_f64x2_promote_low_f32x4_zero:
5834+
{
5835+
wasm_set_exception(module, "unsupported SIMD opcode");
5836+
break;
5837+
}
5838+
5839+
/* i8x16 operations */
5840+
case SIMD_i8x16_abs:
5841+
case SIMD_i8x16_neg:
5842+
case SIMD_i8x16_popcnt:
5843+
case SIMD_i8x16_all_true:
5844+
case SIMD_i8x16_bitmask:
5845+
case SIMD_i8x16_narrow_i16x8_s:
5846+
case SIMD_i8x16_narrow_i16x8_u:
5847+
case SIMD_f32x4_ceil:
5848+
case SIMD_f32x4_floor:
5849+
case SIMD_f32x4_trunc:
5850+
case SIMD_f32x4_nearest:
5851+
case SIMD_i8x16_shl:
5852+
case SIMD_i8x16_shr_s:
5853+
case SIMD_i8x16_shr_u:
5854+
case SIMD_i8x16_add:
5855+
case SIMD_i8x16_add_sat_s:
5856+
case SIMD_i8x16_add_sat_u:
5857+
case SIMD_i8x16_sub:
5858+
case SIMD_i8x16_sub_sat_s:
5859+
case SIMD_i8x16_sub_sat_u:
5860+
case SIMD_f64x2_ceil:
5861+
case SIMD_f64x2_floor:
5862+
case SIMD_i8x16_min_s:
5863+
case SIMD_i8x16_min_u:
5864+
case SIMD_i8x16_max_s:
5865+
case SIMD_i8x16_max_u:
5866+
case SIMD_f64x2_trunc:
5867+
case SIMD_i8x16_avgr_u:
5868+
case SIMD_i16x8_extadd_pairwise_i8x16_s:
5869+
case SIMD_i16x8_extadd_pairwise_i8x16_u:
5870+
case SIMD_i32x4_extadd_pairwise_i16x8_s:
5871+
case SIMD_i32x4_extadd_pairwise_i16x8_u:
5872+
{
5873+
wasm_set_exception(module, "unsupported SIMD opcode");
5874+
break;
5875+
}
5876+
5877+
/* i16x8 operations */
5878+
case SIMD_i16x8_abs:
5879+
case SIMD_i16x8_neg:
5880+
case SIMD_i16x8_q15mulr_sat_s:
5881+
case SIMD_i16x8_all_true:
5882+
case SIMD_i16x8_bitmask:
5883+
case SIMD_i16x8_narrow_i32x4_s:
5884+
case SIMD_i16x8_narrow_i32x4_u:
5885+
case SIMD_i16x8_extend_low_i8x16_s:
5886+
case SIMD_i16x8_extend_high_i8x16_s:
5887+
case SIMD_i16x8_extend_low_i8x16_u:
5888+
case SIMD_i16x8_extend_high_i8x16_u:
5889+
case SIMD_i16x8_shl:
5890+
case SIMD_i16x8_shr_s:
5891+
case SIMD_i16x8_shr_u:
5892+
case SIMD_i16x8_add:
5893+
case SIMD_i16x8_add_sat_s:
5894+
case SIMD_i16x8_add_sat_u:
5895+
case SIMD_i16x8_sub:
5896+
case SIMD_i16x8_sub_sat_s:
5897+
case SIMD_i16x8_sub_sat_u:
5898+
case SIMD_f64x2_nearest:
5899+
case SIMD_i16x8_mul:
5900+
case SIMD_i16x8_min_s:
5901+
case SIMD_i16x8_min_u:
5902+
case SIMD_i16x8_max_s:
5903+
case SIMD_i16x8_max_u:
5904+
case SIMD_i16x8_avgr_u:
5905+
case SIMD_i16x8_extmul_low_i8x16_s:
5906+
case SIMD_i16x8_extmul_high_i8x16_s:
5907+
case SIMD_i16x8_extmul_low_i8x16_u:
5908+
case SIMD_i16x8_extmul_high_i8x16_u:
5909+
{
5910+
wasm_set_exception(module, "unsupported SIMD opcode");
5911+
break;
5912+
}
5913+
5914+
/* i32x4 operations */
5915+
case SIMD_i32x4_abs:
5916+
case SIMD_i32x4_neg:
5917+
case SIMD_i32x4_all_true:
5918+
case SIMD_i32x4_bitmask:
5919+
case SIMD_i32x4_extend_low_i16x8_s:
5920+
case SIMD_i32x4_extend_high_i16x8_s:
5921+
case SIMD_i32x4_extend_low_i16x8_u:
5922+
case SIMD_i32x4_extend_high_i16x8_u:
5923+
case SIMD_i32x4_shl:
5924+
case SIMD_i32x4_shr_s:
5925+
case SIMD_i32x4_shr_u:
5926+
case SIMD_i32x4_add:
5927+
case SIMD_i32x4_sub:
5928+
case SIMD_i32x4_mul:
5929+
case SIMD_i32x4_min_s:
5930+
case SIMD_i32x4_min_u:
5931+
case SIMD_i32x4_max_s:
5932+
case SIMD_i32x4_max_u:
5933+
case SIMD_i32x4_dot_i16x8_s:
5934+
case SIMD_i32x4_extmul_low_i16x8_s:
5935+
case SIMD_i32x4_extmul_high_i16x8_s:
5936+
case SIMD_i32x4_extmul_low_i16x8_u:
5937+
case SIMD_i32x4_extmul_high_i16x8_u:
5938+
{
5939+
wasm_set_exception(module, "unsupported SIMD opcode");
5940+
break;
5941+
}
5942+
5943+
/* i64x2 operations */
5944+
case SIMD_i64x2_abs:
5945+
case SIMD_i64x2_neg:
5946+
case SIMD_i64x2_all_true:
5947+
case SIMD_i64x2_bitmask:
5948+
case SIMD_i64x2_extend_low_i32x4_s:
5949+
case SIMD_i64x2_extend_high_i32x4_s:
5950+
case SIMD_i64x2_extend_low_i32x4_u:
5951+
case SIMD_i64x2_extend_high_i32x4_u:
5952+
case SIMD_i64x2_shl:
5953+
case SIMD_i64x2_shr_s:
5954+
case SIMD_i64x2_shr_u:
5955+
case SIMD_i64x2_add:
5956+
case SIMD_i64x2_sub:
5957+
case SIMD_i64x2_mul:
5958+
case SIMD_i64x2_eq:
5959+
case SIMD_i64x2_ne:
5960+
case SIMD_i64x2_lt_s:
5961+
case SIMD_i64x2_gt_s:
5962+
case SIMD_i64x2_le_s:
5963+
case SIMD_i64x2_ge_s:
5964+
case SIMD_i64x2_extmul_low_i32x4_s:
5965+
case SIMD_i64x2_extmul_high_i32x4_s:
5966+
case SIMD_i64x2_extmul_low_i32x4_u:
5967+
case SIMD_i64x2_extmul_high_i32x4_u:
5968+
{
5969+
wasm_set_exception(module, "unsupported SIMD opcode");
5970+
break;
5971+
}
5972+
5973+
/* f32x4 opertions */
5974+
case SIMD_f32x4_abs:
5975+
case SIMD_f32x4_neg:
5976+
case SIMD_f32x4_sqrt:
5977+
case SIMD_f32x4_add:
5978+
case SIMD_f32x4_sub:
5979+
case SIMD_f32x4_mul:
5980+
case SIMD_f32x4_div:
5981+
case SIMD_f32x4_min:
5982+
case SIMD_f32x4_max:
5983+
case SIMD_f32x4_pmin:
5984+
case SIMD_f32x4_pmax:
5985+
{
5986+
wasm_set_exception(module, "unsupported SIMD opcode");
5987+
break;
5988+
}
5989+
5990+
/* f64x2 operations */
5991+
case SIMD_f64x2_abs:
5992+
case SIMD_f64x2_neg:
5993+
case SIMD_f64x2_sqrt:
5994+
case SIMD_f64x2_add:
5995+
case SIMD_f64x2_sub:
5996+
case SIMD_f64x2_mul:
5997+
case SIMD_f64x2_div:
5998+
case SIMD_f64x2_min:
5999+
case SIMD_f64x2_max:
6000+
case SIMD_f64x2_pmin:
6001+
case SIMD_f64x2_pmax:
6002+
{
6003+
wasm_set_exception(module, "unsupported SIMD opcode");
6004+
break;
6005+
}
6006+
6007+
/* Conversion operations */
6008+
case SIMD_i32x4_trunc_sat_f32x4_s:
6009+
case SIMD_i32x4_trunc_sat_f32x4_u:
6010+
case SIMD_f32x4_convert_i32x4_s:
6011+
case SIMD_f32x4_convert_i32x4_u:
6012+
case SIMD_i32x4_trunc_sat_f64x2_s_zero:
6013+
case SIMD_i32x4_trunc_sat_f64x2_u_zero:
6014+
case SIMD_f64x2_convert_low_i32x4_s:
6015+
case SIMD_f64x2_convert_low_i32x4_u:
6016+
{
6017+
wasm_set_exception(module, "unsupported SIMD opcode");
6018+
break;
6019+
}
6020+
56736021
default:
56746022
wasm_set_exception(module, "unsupported SIMD opcode");
56756023
}

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