I open-sourced an ML model that predicts chip design outcomes — 92% accuracy on real OpenLane runs

[n57d30top]

Hey everyone,

If you use OpenLane, you know the loop: tweak config → run → wait 30 minutes → it fails → repeat. Most of that time is wasted because the signs of failure were there from the start.

I built Open Silicon Triage — three simple tools that check your run at every stage:

🔍 1. Before your run — Config Check

Point it at your config.json before you even start:

python cli/analyze-config.py --config ./openlane/config.json
It checks your clock period, utilization, die area, and their combinations against known-good ranges. If you're trying 70% utilization with a 10 ns clock on sky130 — it tells you upfront that's the #1 cause of failed runs.

⏱️ 2. During your run — Early Abort (~5 min in)

After placement finishes, check if the rest is worth it:

python cli/early-check.py --run-dir ./runs/RUN_2026.03.27
If setup WNS is already -18 ns after placement, routing won't fix that. Abort now, save 25 minutes.

📊 3. After your run — Benchmark

Compare your results against the community corpus:

python cli/benchmark.py --run-dir ./runs/RUN_2026.03.27
Shows your metrics vs. community percentiles: "Your HPWL is better than 75% of runs. Your setup violations are in the bottom quartile."

🤝 The community part
All of this gets better with more data. After your run, one command submits your (anonymized) results:

python cli/submit.py --variant "my-design"
The script reads your run folder, extracts the metrics, strips all local paths, and opens a PR. Your design files stay completely private — only anonymous performance numbers are shared.

At 76 records it already gives useful comparisons. At 1,000+ it becomes a real reference database. Failed runs are just as valuable — they teach everyone what to avoid.

GitHub: https://github.com/n57d30top/open-silicon-triage

No ML dependencies needed for the config check and benchmark tools — just Python 3. Happy to answer questions. 🙏