@@ -2247,12 +2247,12 @@ module Impl<FullStateConfigSig Config> {
22472247 Typ getTyp ( DataFlowType t ) { result = t }
22482248
22492249 bindingset [ tc, t, tail]
2250- Ap apCons ( TypedContent tc , Typ t , Ap tail ) { result .getHead ( ) = tc and exists ( t ) and exists ( tail ) }
2250+ Ap apCons ( TypedContent tc , Typ t , Ap tail ) { result .getHead ( ) = tc . getContent ( ) and exists ( t ) and exists ( tail ) }
22512251
22522252 class ApHeadContent = Content ;
22532253
22542254 pragma [ noinline]
2255- ApHeadContent getHeadContent ( Ap ap ) { result = ap .getHead ( ) . getContent ( ) }
2255+ ApHeadContent getHeadContent ( Ap ap ) { result = ap .getHead ( ) }
22562256
22572257 ApHeadContent projectToHeadContent ( Content c ) { result = c }
22582258
@@ -2313,15 +2313,15 @@ module Impl<FullStateConfigSig Config> {
23132313 }
23142314
23152315 pragma [ nomagic]
2316- private predicate clear ( NodeEx node , Ap ap ) { clearContent ( node , ap .getHead ( ) . getContent ( ) ) }
2316+ private predicate clear ( NodeEx node , Ap ap ) { clearContent ( node , ap .getHead ( ) ) }
23172317
23182318 pragma [ nomagic]
23192319 private predicate expectsContentCand ( NodeEx node , Ap ap ) {
23202320 exists ( Content c |
23212321 PrevStage:: revFlow ( node ) and
23222322 PrevStage:: readStepCand ( _, c , _) and
23232323 expectsContentEx ( node , c ) and
2324- c = ap .getHead ( ) . getContent ( )
2324+ c = ap .getHead ( )
23252325 )
23262326 }
23272327
@@ -2372,9 +2372,9 @@ module Impl<FullStateConfigSig Config> {
23722372 tails = strictcount ( DataFlowType t , AccessPathFront apf | Stage4:: consCand ( tc , t , apf ) ) and
23732373 nodes =
23742374 strictcount ( NodeEx n , FlowState state |
2375- Stage4:: revFlow ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc ) )
2375+ Stage4:: revFlow ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc . getContent ( ) ) )
23762376 or
2377- flowCandSummaryCtx ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc ) )
2377+ flowCandSummaryCtx ( n , state , any ( AccessPathFrontHead apf | apf .getHead ( ) = tc . getContent ( ) ) )
23782378 ) and
23792379 accessPathApproxCostLimits ( apLimit , tupleLimit ) and
23802380 apLimit < tails and
@@ -2390,7 +2390,7 @@ module Impl<FullStateConfigSig Config> {
23902390 not expensiveLen2unfolding ( tc )
23912391 } or
23922392 TConsCons ( TypedContent tc1 , DataFlowType t , TypedContent tc2 , int len ) {
2393- Stage4:: consCand ( tc1 , t , TFrontHead ( tc2 ) ) and
2393+ Stage4:: consCand ( tc1 , t , TFrontHead ( tc2 . getContent ( ) ) ) and
23942394 len in [ 2 .. accessPathLimit ( ) ] and
23952395 not expensiveLen2unfolding ( tc1 )
23962396 } or
@@ -2448,7 +2448,7 @@ module Impl<FullStateConfigSig Config> {
24482448
24492449 override int len ( ) { result = 1 }
24502450
2451- override AccessPathFront getFront ( ) { result = TFrontHead ( tc ) }
2451+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc . getContent ( ) ) }
24522452
24532453 override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) { head = tc and typ = t and tail = TNil ( ) }
24542454 }
@@ -2471,7 +2471,7 @@ module Impl<FullStateConfigSig Config> {
24712471
24722472 override int len ( ) { result = len }
24732473
2474- override AccessPathFront getFront ( ) { result = TFrontHead ( tc1 ) }
2474+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc1 . getContent ( ) ) }
24752475
24762476 override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) {
24772477 head = tc1 and
@@ -2503,12 +2503,12 @@ module Impl<FullStateConfigSig Config> {
25032503
25042504 override int len ( ) { result = len }
25052505
2506- override AccessPathFront getFront ( ) { result = TFrontHead ( tc ) }
2506+ override AccessPathFront getFront ( ) { result = TFrontHead ( tc . getContent ( ) ) }
25072507
25082508 override predicate isCons ( TypedContent head , DataFlowType typ , AccessPathApprox tail ) {
25092509 head = tc and
25102510 (
2511- exists ( TypedContent tc2 | Stage4:: consCand ( tc , typ , TFrontHead ( tc2 ) ) |
2511+ exists ( TypedContent tc2 | Stage4:: consCand ( tc , typ , TFrontHead ( tc2 . getContent ( ) ) ) |
25122512 tail = TConsCons ( tc2 , _, _, len - 1 )
25132513 or
25142514 len = 2 and
@@ -2884,7 +2884,7 @@ module Impl<FullStateConfigSig Config> {
28842884 head = head_ and typ = t and tail = tail_
28852885 }
28862886
2887- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ ) }
2887+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ . getContent ( ) ) }
28882888
28892889 pragma [ assume_small_delta]
28902890 override AccessPathApproxCons getApprox ( ) {
@@ -2949,7 +2949,7 @@ module Impl<FullStateConfigSig Config> {
29492949 tail .length ( ) = len - 1
29502950 }
29512951
2952- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head1 ) }
2952+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head1 . getContent ( ) ) }
29532953
29542954 override AccessPathApproxCons getApprox ( ) {
29552955 result = TConsCons ( head1 , t , head2 , len ) or
@@ -2984,7 +2984,7 @@ module Impl<FullStateConfigSig Config> {
29842984 Stage5:: consCand ( head_ , typ , tail .getApprox ( ) ) and tail .length ( ) = len - 1
29852985 }
29862986
2987- override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ ) }
2987+ override AccessPathFrontHead getFront ( ) { result = TFrontHead ( head_ . getContent ( ) ) }
29882988
29892989 override AccessPathApproxCons getApprox ( ) { result = TCons1 ( head_ , len ) }
29902990
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