Skip to content

Commit a7f7221

Browse files
RalfJungRalfJung
committed
slightly adjust and synchronize Machine passing for SB and DataRace
1 parent f479404 commit a7f7221

3 files changed

Lines changed: 24 additions & 55 deletions

File tree

‎src/tools/miri/src/concurrency/data_race.rs‎

Lines changed: 12 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -838,18 +838,18 @@ impl VClockAlloc {
838838
&self,
839839
alloc_id: AllocId,
840840
range: AllocRange,
841-
global: &GlobalState,
842-
thread_mgr: &ThreadManager<'_, '_>,
841+
machine: &MiriMachine<'_, '_>,
843842
) -> InterpResult<'tcx> {
843+
let global = machine.data_race.as_ref().unwrap();
844844
if global.race_detecting() {
845-
let (index, clocks) = global.current_thread_state(thread_mgr);
845+
let (index, clocks) = global.current_thread_state(&machine.threads);
846846
let mut alloc_ranges = self.alloc_ranges.borrow_mut();
847847
for (offset, range) in alloc_ranges.iter_mut(range.start, range.size) {
848848
if let Err(DataRace) = range.read_race_detect(&clocks, index) {
849849
// Report data-race.
850850
return Self::report_data_race(
851851
global,
852-
thread_mgr,
852+
&machine.threads,
853853
range,
854854
"Read",
855855
false,
@@ -869,17 +869,17 @@ impl VClockAlloc {
869869
alloc_id: AllocId,
870870
range: AllocRange,
871871
write_type: WriteType,
872-
global: &mut GlobalState,
873-
thread_mgr: &ThreadManager<'_, '_>,
872+
machine: &mut MiriMachine<'_, '_>,
874873
) -> InterpResult<'tcx> {
874+
let global = machine.data_race.as_mut().unwrap();
875875
if global.race_detecting() {
876-
let (index, clocks) = global.current_thread_state(thread_mgr);
876+
let (index, clocks) = global.current_thread_state(&machine.threads);
877877
for (offset, range) in self.alloc_ranges.get_mut().iter_mut(range.start, range.size) {
878878
if let Err(DataRace) = range.write_race_detect(&clocks, index, write_type) {
879879
// Report data-race
880880
return Self::report_data_race(
881881
global,
882-
thread_mgr,
882+
&machine.threads,
883883
range,
884884
write_type.get_descriptor(),
885885
false,
@@ -901,10 +901,9 @@ impl VClockAlloc {
901901
&mut self,
902902
alloc_id: AllocId,
903903
range: AllocRange,
904-
global: &mut GlobalState,
905-
thread_mgr: &ThreadManager<'_, '_>,
904+
machine: &mut MiriMachine<'_, '_>,
906905
) -> InterpResult<'tcx> {
907-
self.unique_access(alloc_id, range, WriteType::Write, global, thread_mgr)
906+
self.unique_access(alloc_id, range, WriteType::Write, machine)
908907
}
909908

910909
/// Detect data-races for an unsynchronized deallocate operation, will not perform
@@ -915,10 +914,9 @@ impl VClockAlloc {
915914
&mut self,
916915
alloc_id: AllocId,
917916
range: AllocRange,
918-
global: &mut GlobalState,
919-
thread_mgr: &ThreadManager<'_, '_>,
917+
machine: &mut MiriMachine<'_, '_>,
920918
) -> InterpResult<'tcx> {
921-
self.unique_access(alloc_id, range, WriteType::Deallocate, global, thread_mgr)
919+
self.unique_access(alloc_id, range, WriteType::Deallocate, machine)
922920
}
923921
}
924922

‎src/tools/miri/src/machine.rs‎

Lines changed: 7 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -1003,21 +1003,12 @@ impl<'mir, 'tcx> Machine<'mir, 'tcx> for MiriMachine<'mir, 'tcx> {
10031003
range: AllocRange,
10041004
) -> InterpResult<'tcx> {
10051005
if let Some(data_race) = &alloc_extra.data_race {
1006-
data_race.read(
1007-
alloc_id,
1008-
range,
1009-
machine.data_race.as_ref().unwrap(),
1010-
&machine.threads,
1011-
)?;
1006+
data_race.read(alloc_id, range, machine)?;
10121007
}
10131008
if let Some(stacked_borrows) = &alloc_extra.stacked_borrows {
1014-
stacked_borrows.borrow_mut().before_memory_read(
1015-
alloc_id,
1016-
prov_extra,
1017-
range,
1018-
machine.stacked_borrows.as_ref().unwrap(),
1019-
machine,
1020-
)?;
1009+
stacked_borrows
1010+
.borrow_mut()
1011+
.before_memory_read(alloc_id, prov_extra, range, machine)?;
10211012
}
10221013
if let Some(weak_memory) = &alloc_extra.weak_memory {
10231014
weak_memory.memory_accessed(range, machine.data_race.as_ref().unwrap());
@@ -1034,21 +1025,10 @@ impl<'mir, 'tcx> Machine<'mir, 'tcx> for MiriMachine<'mir, 'tcx> {
10341025
range: AllocRange,
10351026
) -> InterpResult<'tcx> {
10361027
if let Some(data_race) = &mut alloc_extra.data_race {
1037-
data_race.write(
1038-
alloc_id,
1039-
range,
1040-
machine.data_race.as_mut().unwrap(),
1041-
&machine.threads,
1042-
)?;
1028+
data_race.write(alloc_id, range, machine)?;
10431029
}
10441030
if let Some(stacked_borrows) = &mut alloc_extra.stacked_borrows {
1045-
stacked_borrows.get_mut().before_memory_write(
1046-
alloc_id,
1047-
prov_extra,
1048-
range,
1049-
machine.stacked_borrows.as_ref().unwrap(),
1050-
machine,
1051-
)?;
1031+
stacked_borrows.get_mut().before_memory_write(alloc_id, prov_extra, range, machine)?;
10521032
}
10531033
if let Some(weak_memory) = &alloc_extra.weak_memory {
10541034
weak_memory.memory_accessed(range, machine.data_race.as_ref().unwrap());
@@ -1068,19 +1048,13 @@ impl<'mir, 'tcx> Machine<'mir, 'tcx> for MiriMachine<'mir, 'tcx> {
10681048
machine.emit_diagnostic(NonHaltingDiagnostic::FreedAlloc(alloc_id));
10691049
}
10701050
if let Some(data_race) = &mut alloc_extra.data_race {
1071-
data_race.deallocate(
1072-
alloc_id,
1073-
range,
1074-
machine.data_race.as_mut().unwrap(),
1075-
&machine.threads,
1076-
)?;
1051+
data_race.deallocate(alloc_id, range, machine)?;
10771052
}
10781053
if let Some(stacked_borrows) = &mut alloc_extra.stacked_borrows {
10791054
stacked_borrows.get_mut().before_memory_deallocation(
10801055
alloc_id,
10811056
prove_extra,
10821057
range,
1083-
machine.stacked_borrows.as_ref().unwrap(),
10841058
machine,
10851059
)
10861060
} else {

‎src/tools/miri/src/stacked_borrows/mod.rs‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -644,7 +644,6 @@ impl Stacks {
644644
alloc_id: AllocId,
645645
tag: ProvenanceExtra,
646646
range: AllocRange,
647-
state: &GlobalState,
648647
machine: &'ecx MiriMachine<'mir, 'tcx>,
649648
) -> InterpResult<'tcx>
650649
where
@@ -657,7 +656,7 @@ impl Stacks {
657656
range.size.bytes()
658657
);
659658
let dcx = DiagnosticCxBuilder::read(machine, tag, range);
660-
let state = state.borrow();
659+
let state = machine.stacked_borrows.as_ref().unwrap().borrow();
661660
self.for_each(range, dcx, |stack, dcx, exposed_tags| {
662661
stack.access(AccessKind::Read, tag, &state, dcx, exposed_tags)
663662
})
@@ -669,8 +668,7 @@ impl Stacks {
669668
alloc_id: AllocId,
670669
tag: ProvenanceExtra,
671670
range: AllocRange,
672-
state: &GlobalState,
673-
machine: &'ecx MiriMachine<'mir, 'tcx>,
671+
machine: &'ecx mut MiriMachine<'mir, 'tcx>,
674672
) -> InterpResult<'tcx> {
675673
trace!(
676674
"write access with tag {:?}: {:?}, size {}",
@@ -679,7 +677,7 @@ impl Stacks {
679677
range.size.bytes()
680678
);
681679
let dcx = DiagnosticCxBuilder::write(machine, tag, range);
682-
let state = state.borrow();
680+
let state = machine.stacked_borrows.as_ref().unwrap().borrow();
683681
self.for_each(range, dcx, |stack, dcx, exposed_tags| {
684682
stack.access(AccessKind::Write, tag, &state, dcx, exposed_tags)
685683
})
@@ -691,12 +689,11 @@ impl Stacks {
691689
alloc_id: AllocId,
692690
tag: ProvenanceExtra,
693691
range: AllocRange,
694-
state: &GlobalState,
695-
machine: &'ecx MiriMachine<'mir, 'tcx>,
692+
machine: &'ecx mut MiriMachine<'mir, 'tcx>,
696693
) -> InterpResult<'tcx> {
697694
trace!("deallocation with tag {:?}: {:?}, size {}", tag, alloc_id, range.size.bytes());
698695
let dcx = DiagnosticCxBuilder::dealloc(machine, tag);
699-
let state = state.borrow();
696+
let state = machine.stacked_borrows.as_ref().unwrap().borrow();
700697
self.for_each(range, dcx, |stack, dcx, exposed_tags| {
701698
stack.dealloc(tag, &state, dcx, exposed_tags)
702699
})?;

0 commit comments

Comments
 (0)