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clk: mediatek: Add MT8196 vencsys clock support
Add support for the MT8196 vencsys clock controller, which provides clock gate control for the video encoder. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig‎

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@@ -1066,6 +1066,13 @@ config COMMON_CLK_MT8196_VDECSYS
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help
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This driver supports MediaTek MT8196 vdecsys clocks.
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config COMMON_CLK_MT8196_VENCSYS
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tristate "Clock driver for MediaTek MT8196 vencsys"
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depends on COMMON_CLK_MT8196
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default m
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help
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This driver supports MediaTek MT8196 vencsys clocks.
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config COMMON_CLK_MT8365
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tristate "Clock driver for MediaTek MT8365"
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depends on ARCH_MEDIATEK || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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@@ -162,6 +162,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o c
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8196_VENCSYS) += clk-mt8196-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
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obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o

‎drivers/clk/mediatek/clk-mt8196-venc.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs ven10_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs ven10_hwv_regs = {
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.set_ofs = 0x00b8,
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.clr_ofs = 0x00bc,
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.sta_ofs = 0x2c5c,
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};
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static const struct mtk_gate_regs ven11_cg_regs = {
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.set_ofs = 0x10,
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.clr_ofs = 0x14,
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.sta_ofs = 0x10,
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};
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static const struct mtk_gate_regs ven11_hwv_regs = {
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.set_ofs = 0x00c0,
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.clr_ofs = 0x00c4,
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.sta_ofs = 0x2c60,
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};
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#define GATE_VEN10(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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#define GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, _flags) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven10_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
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.flags = (_flags) | \
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CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN10(_id, _name, _parent, _shift) \
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GATE_HWV_VEN10_FLAGS(_id, _name, _parent, _shift, 0)
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#define GATE_HWV_VEN11(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven11_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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static const struct mtk_gate ven1_clks[] = {
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/* VEN10 */
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GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
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GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
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GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
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GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
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GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
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GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
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GATE_HWV_VEN10(CLK_VEN1_CKE29_VENC_ADAB_CTRL, "ven1_venc_adab_ctrl",
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"venc", 29),
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GATE_HWV_VEN10_FLAGS(CLK_VEN1_CKE29_VENC_XPC_CTRL,
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"ven1_venc_xpc_ctrl", "venc", 30,
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CLK_IGNORE_UNUSED),
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GATE_HWV_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc", 31),
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/* VEN11 */
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GATE_HWV_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "venc", 0),
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};
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static const struct mtk_clk_desc ven1_mcd = {
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.clks = ven1_clks,
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.num_clks = ARRAY_SIZE(ven1_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate_regs ven20_hwv_regs = {
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.set_ofs = 0x00c8,
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.clr_ofs = 0x00cc,
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.sta_ofs = 0x2c64,
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};
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static const struct mtk_gate_regs ven21_hwv_regs = {
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.set_ofs = 0x00d0,
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.clr_ofs = 0x00d4,
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.sta_ofs = 0x2c68,
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};
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#define GATE_VEN20(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.shift = _shift, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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#define GATE_HWV_VEN20(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven20_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN21(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven21_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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static const struct mtk_gate ven2_clks[] = {
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/* VEN20 */
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GATE_HWV_VEN20(CLK_VEN2_CKE0_LARB, "ven2_larb", "venc", 0),
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GATE_HWV_VEN20(CLK_VEN2_CKE1_VENC, "ven2_venc", "venc", 4),
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GATE_VEN20(CLK_VEN2_CKE2_JPGENC, "ven2_jpgenc", "venc", 8),
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GATE_VEN20(CLK_VEN2_CKE3_JPGDEC, "ven2_jpgdec", "venc", 12),
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GATE_HWV_VEN20(CLK_VEN2_CKE5_GALS, "ven2_gals", "venc", 28),
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GATE_HWV_VEN20(CLK_VEN2_CKE29_VENC_XPC_CTRL, "ven2_venc_xpc_ctrl", "venc", 30),
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GATE_HWV_VEN20(CLK_VEN2_CKE6_GALS_SRAM, "ven2_gals_sram", "venc", 31),
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/* VEN21 */
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GATE_HWV_VEN21(CLK_VEN2_RES_FLAT, "ven2_res_flat", "venc", 0),
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};
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static const struct mtk_clk_desc ven2_mcd = {
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.clks = ven2_clks,
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.num_clks = ARRAY_SIZE(ven2_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate_regs ven_c20_hwv_regs = {
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.set_ofs = 0x00d8,
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.clr_ofs = 0x00dc,
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.sta_ofs = 0x2c6c,
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};
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static const struct mtk_gate_regs ven_c21_hwv_regs = {
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.set_ofs = 0x00e0,
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.clr_ofs = 0x00e4,
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.sta_ofs = 0x2c70,
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};
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#define GATE_HWV_VEN_C20(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven10_cg_regs, \
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.hwv_regs = &ven_c20_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VEN_C21(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ven11_cg_regs, \
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.hwv_regs = &ven_c21_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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static const struct mtk_gate ven_c2_clks[] = {
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/* VEN_C20 */
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE0_LARB, "ven_c2_larb", "venc", 0),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE1_VENC, "ven_c2_venc", "venc", 4),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE5_GALS, "ven_c2_gals", "venc", 28),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE29_VENC_XPC_CTRL, "ven_c2_venc_xpc_ctrl",
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"venc", 30),
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GATE_HWV_VEN_C20(CLK_VEN_C2_CKE6_GALS_SRAM, "ven_c2_gals_sram", "venc", 31),
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/* VEN_C21 */
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GATE_HWV_VEN_C21(CLK_VEN_C2_RES_FLAT, "ven_c2_res_flat", "venc", 0),
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};
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static const struct mtk_clk_desc ven_c2_mcd = {
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.clks = ven_c2_clks,
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.num_clks = ARRAY_SIZE(ven_c2_clks),
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.need_runtime_pm = true,
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};
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static const struct of_device_id of_match_clk_mt8196_venc[] = {
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{ .compatible = "mediatek,mt8196-vencsys", .data = &ven1_mcd },
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{ .compatible = "mediatek,mt8196-vencsys-c1", .data = &ven2_mcd },
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{ .compatible = "mediatek,mt8196-vencsys-c2", .data = &ven_c2_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_venc);
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static struct platform_driver clk_mt8196_venc_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-venc",
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.of_match_table = of_match_clk_mt8196_venc,
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},
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};
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module_platform_driver(clk_mt8196_venc_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 Video Encoders clocks driver");
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MODULE_LICENSE("GPL");

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