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tq-niebelmShawn Guo
tq-niebelm
authored and
Shawn Guo
committed
arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off
Fix SD card removal caused by automatic LDO5 power off after boot: LDO5: disabling mmc1: card 59b4 removed EXT4-fs (mmcblk1p2): shut down requested (2) Aborting journal on device mmcblk1p2-8. JBD2: I/O error when updating journal superblock for mmcblk1p2-8. To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled regulator that is supplied by LDO5. Since this is implemented on SoM but used on baseboards with SD-card interface, implement the functionality on SoM part and optionally enable it on baseboards if needed. Fixes: 418d1d8 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP") Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
1 parent 8f5ae30 commit 5245dc5

3 files changed

Lines changed: 36 additions & 12 deletions

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‎arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -467,6 +467,10 @@
467467
status = "okay";
468468
};
469469

470+
&reg_usdhc2_vqmmc {
471+
status = "okay";
472+
};
473+
470474
&sai5 {
471475
pinctrl-names = "default";
472476
pinctrl-0 = <&pinctrl_sai5>;
@@ -876,8 +880,7 @@
876880
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
877881
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
878882
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
879-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
880-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
883+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>;
881884
};
882885

883886
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -886,8 +889,7 @@
886889
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
887890
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
888891
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
889-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
890-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
892+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
891893
};
892894

893895
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -896,8 +898,7 @@
896898
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
897899
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
898900
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
899-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
900-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
901+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
901902
};
902903

903904
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

‎arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -604,6 +604,10 @@
604604
status = "okay";
605605
};
606606

607+
&reg_usdhc2_vqmmc {
608+
status = "okay";
609+
};
610+
607611
&sai3 {
608612
pinctrl-names = "default";
609613
pinctrl-0 = <&pinctrl_sai3>;
@@ -983,8 +987,7 @@
983987
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>,
984988
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>,
985989
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>,
986-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>,
987-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
990+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>;
988991
};
989992

990993
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -993,8 +996,7 @@
993996
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
994997
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
995998
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
996-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
997-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
999+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
9981000
};
9991001

10001002
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -1003,8 +1005,7 @@
10031005
<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
10041006
<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
10051007
<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1006-
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>,
1007-
<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>;
1008+
<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
10081009
};
10091010

10101011
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

‎arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,20 @@
2424
regulator-max-microvolt = <3300000>;
2525
regulator-always-on;
2626
};
27+
28+
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
29+
compatible = "regulator-gpio";
30+
pinctrl-names = "default";
31+
pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
32+
regulator-name = "V_SD2";
33+
regulator-min-microvolt = <1800000>;
34+
regulator-max-microvolt = <3300000>;
35+
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
36+
states = <1800000 0x1>,
37+
<3300000 0x0>;
38+
vin-supply = <&ldo5_reg>;
39+
status = "disabled";
40+
};
2741
};
2842

2943
&A53_0 {
@@ -184,6 +198,10 @@
184198
};
185199
};
186200

201+
&usdhc2 {
202+
vqmmc-supply = <&reg_usdhc2_vqmmc>;
203+
};
204+
187205
&usdhc3 {
188206
pinctrl-names = "default", "state_100mhz", "state_200mhz";
189207
pinctrl-0 = <&pinctrl_usdhc3>;
@@ -233,6 +251,10 @@
233251
fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x10>;
234252
};
235253

254+
pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
255+
fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0>;
256+
};
257+
236258
pinctrl_usdhc3: usdhc3grp {
237259
fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
238260
<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>,

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