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Merge tag 'renesas-r9a09g077-dt-binding-defs-tag3' into renesas-pinctrl-for-v6.18
Renesas RZ/T2H and RZ/N2H USB_CLK and Pin Control DT Binding Definitions USB_CLK Clock and Pin Control DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
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‎Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
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maintainers:
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- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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description:
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The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
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Pin multiplexing and GPIO configuration are performed on a per-pin basis.
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Each port supports up to 8 pins, each configurable for either GPIO (port mode)
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or alternate function mode. Each pin supports function mode values ranging from
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0x0 to 0x2A, allowing selection from up to 43 different functions.
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properties:
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compatible:
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enum:
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- renesas,r9a09g077-pinctrl # RZ/T2H
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- renesas,r9a09g087-pinctrl # RZ/N2H
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reg:
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minItems: 1
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items:
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- description: Non-safety I/O Port base
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- description: Safety I/O Port safety region base
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- description: Safety I/O Port Non-safety region base
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reg-names:
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minItems: 1
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items:
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- const: nsr
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- const: srs
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- const: srn
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gpio-controller: true
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'#gpio-cells':
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const: 2
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description:
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The first cell contains the global GPIO port index, constructed using the
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RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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(e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
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flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
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gpio-ranges:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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definitions:
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renesas-rzt2h-n2h-pins-node:
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type: object
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allOf:
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- $ref: pincfg-node.yaml#
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- $ref: pinmux-node.yaml#
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properties:
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pinmux:
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description:
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Values are constructed from I/O port number, pin number, and
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alternate function configuration number using the RZT2H_PORT_PINMUX()
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helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>.
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pins: true
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phandle: true
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input: true
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input-enable: true
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output-enable: true
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oneOf:
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- required: [pinmux]
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- required: [pins]
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additionalProperties: false
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patternProperties:
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# Grouping nodes: allow multiple "-pins" subnodes within a "-group"
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'.*-group$':
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type: object
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description:
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Pin controller client devices can organize pin configuration entries into
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grouping nodes ending in "-group". These group nodes may contain multiple
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child nodes each ending in "-pins" to configure distinct sets of pins.
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additionalProperties: false
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patternProperties:
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'-pins$':
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$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
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# Standalone "-pins" nodes under client devices or groups
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'-pins$':
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$ref: '#/definitions/renesas-rzt2h-n2h-pins-node'
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'-hog$':
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type: object
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description: GPIO hog node
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properties:
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gpio-hog: true
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gpios: true
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input: true
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output-high: true
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output-low: true
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line-name: true
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required:
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- gpio-hog
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- gpios
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additionalProperties: false
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- reg
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- reg-names
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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- clocks
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
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pinctrl@802c0000 {
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compatible = "renesas,r9a09g077-pinctrl";
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reg = <0x802c0000 0x2000>,
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<0x812c0000 0x2000>,
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<0x802b0000 0x2000>;
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reg-names = "nsr", "srs", "srn";
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clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 288>;
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power-domains = <&cpg>;
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serial0-pins {
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pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */
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<RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */
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};
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sd1-pwr-en-hog {
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gpio-hog;
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gpios = <RZT2H_GPIO(39, 2) 0>;
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output-high;
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line-name = "sd1_pwr_en";
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};
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i2c0-pins {
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pins = "RIIC0_SDA", "RIIC0_SCL";
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input-enable;
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};
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sd0-sd-group {
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ctrl-pins {
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pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
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<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
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};
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data-pins {
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pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
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<RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
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};
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};
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};

‎include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h‎

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#define R9A09G077_CLK_PCLKM 13
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#define R9A09G077_CLK_PCLKL 14
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#define R9A09G077_SDHI_CLKHS 15
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#define R9A09G077_USB_CLK 16
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

‎include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h‎

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#define R9A09G087_CLK_PCLKM 13
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#define R9A09G087_CLK_PCLKL 14
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#define R9A09G087_SDHI_CLKHS 15
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#define R9A09G087_USB_CLK 16
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */

‎include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* This header provides constants for Renesas RZ/T2H family pinctrl bindings.
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
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#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
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#define RZT2H_PINS_PER_PORT 8
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/*
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* Create the pin index from its bank and position numbers and store in
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* the upper 16 bits the alternate function identifier
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*/
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#define RZT2H_PORT_PINMUX(b, p, f) ((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
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/* Convert a port and pin label to its global pin index */
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#define RZT2H_GPIO(port, pin) ((port) * RZT2H_PINS_PER_PORT + (pin))
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#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */

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