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Nicolas FrattaroliYuryNorov
Nicolas Frattaroli
authored and
YuryNorov
committed
drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro
The era of hand-rolled HIWORD_UPDATE macros is over, at least for those drivers that use constant masks. Replace this driver's HIWORD_UPDATE with the FIELD_PREP_WM16 macro from hw_bitfield.h. While at it, disambiguate the GRF write to SOC_CON7 by splitting the definition into the individual bitflags. This is done because FIELD_PREP_WM16 shifts the value for us according to the mask, so writing the mask to itself to enable two bits is no longer something that can be done. It should also not be done anyway because it hides the true meaning of those two individual bit flags. HDMI output with this patch has been tested on both RK3588 and RK3576. On the former, with both present HDMI connectors. Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
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Lines changed: 33 additions & 35 deletions

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‎drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c‎

Lines changed: 33 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99

1010
#include <linux/clk.h>
1111
#include <linux/gpio/consumer.h>
12+
#include <linux/hw_bitfield.h>
1213
#include <linux/mfd/syscon.h>
1314
#include <linux/module.h>
1415
#include <linux/platform_device.h>
@@ -66,7 +67,8 @@
6667
#define RK3588_HDMI1_HPD_INT_MSK BIT(15)
6768
#define RK3588_HDMI1_HPD_INT_CLR BIT(14)
6869
#define RK3588_GRF_SOC_CON7 0x031c
69-
#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12)
70+
#define RK3588_HPD_HDMI0_IO_EN_MASK BIT(12)
71+
#define RK3588_HPD_HDMI1_IO_EN_MASK BIT(13)
7072
#define RK3588_GRF_SOC_STATUS1 0x0384
7173
#define RK3588_HDMI0_LEVEL_INT BIT(16)
7274
#define RK3588_HDMI1_LEVEL_INT BIT(24)
@@ -80,7 +82,6 @@
8082
#define RK3588_HDMI0_GRANT_SEL BIT(10)
8183
#define RK3588_HDMI1_GRANT_SEL BIT(12)
8284

83-
#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
8485
#define HOTPLUG_DEBOUNCE_MS 150
8586
#define MAX_HDMI_PORT_NUM 2
8687

@@ -185,11 +186,11 @@ static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
185186
u32 val;
186187

187188
if (hdmi->port_id)
188-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,
189-
RK3588_HDMI1_HPD_INT_CLR | RK3588_HDMI1_HPD_INT_MSK);
189+
val = (FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1) |
190+
FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0));
190191
else
191-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
192-
RK3588_HDMI0_HPD_INT_CLR | RK3588_HDMI0_HPD_INT_MSK);
192+
val = (FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1) |
193+
FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0));
193194

194195
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
195196
}
@@ -218,8 +219,8 @@ static void dw_hdmi_qp_rk3576_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
218219
struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
219220
u32 val;
220221

221-
val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR,
222-
RK3576_HDMI_HPD_INT_CLR | RK3576_HDMI_HPD_INT_MSK);
222+
val = (FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1) |
223+
FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0));
223224

224225
regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
225226
regmap_write(hdmi->regmap, 0xa404, 0xffff0102);
@@ -254,7 +255,7 @@ static irqreturn_t dw_hdmi_qp_rk3576_hardirq(int irq, void *dev_id)
254255

255256
regmap_read(hdmi->regmap, RK3576_IOC_HDMI_HPD_STATUS, &intr_stat);
256257
if (intr_stat) {
257-
val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_MSK, RK3576_HDMI_HPD_INT_MSK);
258+
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 1);
258259

259260
regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
260261
return IRQ_WAKE_THREAD;
@@ -273,12 +274,12 @@ static irqreturn_t dw_hdmi_qp_rk3576_irq(int irq, void *dev_id)
273274
if (!intr_stat)
274275
return IRQ_NONE;
275276

276-
val = HIWORD_UPDATE(RK3576_HDMI_HPD_INT_CLR, RK3576_HDMI_HPD_INT_CLR);
277+
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_CLR, 1);
277278
regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
278279
mod_delayed_work(system_wq, &hdmi->hpd_work,
279280
msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
280281

281-
val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);
282+
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
282283
regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
283284

284285
return IRQ_HANDLED;
@@ -293,11 +294,9 @@ static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id)
293294

294295
if (intr_stat) {
295296
if (hdmi->port_id)
296-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK,
297-
RK3588_HDMI1_HPD_INT_MSK);
297+
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
298298
else
299-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,
300-
RK3588_HDMI0_HPD_INT_MSK);
299+
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
301300
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
302301
return IRQ_WAKE_THREAD;
303302
}
@@ -315,20 +314,18 @@ static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id)
315314
return IRQ_NONE;
316315

317316
if (hdmi->port_id)
318-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_CLR,
319-
RK3588_HDMI1_HPD_INT_CLR);
317+
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1);
320318
else
321-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
322-
RK3588_HDMI0_HPD_INT_CLR);
319+
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_CLR, 1);
323320
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
324321

325322
mod_delayed_work(system_wq, &hdmi->hpd_work,
326323
msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
327324

328325
if (hdmi->port_id)
329-
val |= HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK);
326+
val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0);
330327
else
331-
val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
328+
val |= FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 0);
332329
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
333330

334331
return IRQ_HANDLED;
@@ -338,42 +335,43 @@ static void dw_hdmi_qp_rk3576_io_init(struct rockchip_hdmi_qp *hdmi)
338335
{
339336
u32 val;
340337

341-
val = HIWORD_UPDATE(RK3576_SCLIN_MASK, RK3576_SCLIN_MASK) |
342-
HIWORD_UPDATE(RK3576_SDAIN_MASK, RK3576_SDAIN_MASK) |
343-
HIWORD_UPDATE(RK3576_HDMI_GRANT_SEL, RK3576_HDMI_GRANT_SEL) |
344-
HIWORD_UPDATE(RK3576_I2S_SEL_MASK, RK3576_I2S_SEL_MASK);
338+
val = FIELD_PREP_WM16(RK3576_SCLIN_MASK, 1) |
339+
FIELD_PREP_WM16(RK3576_SDAIN_MASK, 1) |
340+
FIELD_PREP_WM16(RK3576_HDMI_GRANT_SEL, 1) |
341+
FIELD_PREP_WM16(RK3576_I2S_SEL_MASK, 1);
345342

346343
regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON14, val);
347344

348-
val = HIWORD_UPDATE(0, RK3576_HDMI_HPD_INT_MSK);
345+
val = FIELD_PREP_WM16(RK3576_HDMI_HPD_INT_MSK, 0);
349346
regmap_write(hdmi->regmap, RK3576_IOC_MISC_CON0, val);
350347
}
351348

352349
static void dw_hdmi_qp_rk3588_io_init(struct rockchip_hdmi_qp *hdmi)
353350
{
354351
u32 val;
355352

356-
val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
357-
HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
358-
HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
359-
HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
353+
val = FIELD_PREP_WM16(RK3588_SCLIN_MASK, 1) |
354+
FIELD_PREP_WM16(RK3588_SDAIN_MASK, 1) |
355+
FIELD_PREP_WM16(RK3588_MODE_MASK, 1) |
356+
FIELD_PREP_WM16(RK3588_I2S_SEL_MASK, 1);
360357
regmap_write(hdmi->vo_regmap,
361358
hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3,
362359
val);
363360

364-
val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, RK3588_SET_HPD_PATH_MASK);
361+
val = FIELD_PREP_WM16(RK3588_HPD_HDMI0_IO_EN_MASK, 1) |
362+
FIELD_PREP_WM16(RK3588_HPD_HDMI1_IO_EN_MASK, 1);
365363
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
366364

367365
if (hdmi->port_id)
368-
val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, RK3588_HDMI1_GRANT_SEL);
366+
val = FIELD_PREP_WM16(RK3588_HDMI1_GRANT_SEL, 1);
369367
else
370-
val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, RK3588_HDMI0_GRANT_SEL);
368+
val = FIELD_PREP_WM16(RK3588_HDMI0_GRANT_SEL, 1);
371369
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
372370

373371
if (hdmi->port_id)
374-
val = HIWORD_UPDATE(RK3588_HDMI1_HPD_INT_MSK, RK3588_HDMI1_HPD_INT_MSK);
372+
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 1);
375373
else
376-
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);
374+
val = FIELD_PREP_WM16(RK3588_HDMI0_HPD_INT_MSK, 1);
377375
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
378376
}
379377

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