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Kaustabh Chakrabortydaeinki
Kaustabh Chakraborty
authored and
daeinki
committed
drm/bridge: samsung-dsim: allow configuring bits and offsets of CLKCTRL register
DSIM_CLKCTRL bit and offset values hardcoded in the driver: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 19 DSIM_LANE_ESC_CLK_EN_DATA | 20 DSIM_BYTE_CLKEN | 24 DSIM_ESC_CLKEN | 28 DSIM_TX_REQUEST_HSCLK | 31 DSIM_CLKCTRL bit and offset values in Exynos7870 DSIM as per downstream kernel sources: name | bit/offset value --------------------------+----------------- DSIM_LANE_ESC_CLK_EN_CLK | 8 DSIM_LANE_ESC_CLK_EN_DATA | 9 DSIM_BYTE_CLKEN | 17 DSIM_ESC_CLKEN | 16 DSIM_TX_REQUEST_HSCLK | 20 In order to support both, move all values to the driver data struct and define it for every driver compatible. Reference the values from there instead, in functions wherever required. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
1 parent 92beab1 commit f6ba4c1

2 files changed

Lines changed: 59 additions & 22 deletions

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‎drivers/gpu/drm/bridge/samsung-dsim.c‎

Lines changed: 54 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -46,17 +46,13 @@
4646
#define DSIM_BTA_TIMEOUT(x) ((x) << 16)
4747

4848
/* DSIM_CLKCTRL */
49-
#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
50-
#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
51-
#define DSIM_LANE_ESC_CLK_EN_CLK BIT(19)
52-
#define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
53-
#define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
54-
#define DSIM_BYTE_CLKEN BIT(24)
55-
#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
56-
#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
57-
#define DSIM_PLL_BYPASS BIT(27)
58-
#define DSIM_ESC_CLKEN BIT(28)
59-
#define DSIM_TX_REQUEST_HSCLK BIT(31)
49+
#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
50+
#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
51+
#define DSIM_LANE_ESC_CLK_EN_DATA(x, offset) (((x) & 0xf) << offset)
52+
#define DSIM_LANE_ESC_CLK_EN_DATA_MASK(offset) (0xf << offset)
53+
#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
54+
#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
55+
#define DSIM_PLL_BYPASS BIT(27)
6056

6157
/* DSIM_CONFIG */
6258
#define DSIM_LANE_EN_CLK BIT(0)
@@ -421,6 +417,11 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
421417
.wait_for_hdr_fifo = 1,
422418
.wait_for_reset = 1,
423419
.num_bits_resol = 11,
420+
.esc_clken_bit = 28,
421+
.byte_clken_bit = 24,
422+
.tx_req_hsclk_bit = 31,
423+
.lane_esc_clk_bit = 19,
424+
.lane_esc_data_offset = 20,
424425
.pll_p_offset = 13,
425426
.reg_values = reg_values,
426427
.pll_fin_min = 6,
@@ -442,6 +443,11 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
442443
.wait_for_hdr_fifo = 1,
443444
.wait_for_reset = 1,
444445
.num_bits_resol = 11,
446+
.esc_clken_bit = 28,
447+
.byte_clken_bit = 24,
448+
.tx_req_hsclk_bit = 31,
449+
.lane_esc_clk_bit = 19,
450+
.lane_esc_data_offset = 20,
445451
.pll_p_offset = 13,
446452
.reg_values = reg_values,
447453
.pll_fin_min = 6,
@@ -461,6 +467,11 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
461467
.wait_for_hdr_fifo = 1,
462468
.wait_for_reset = 1,
463469
.num_bits_resol = 11,
470+
.esc_clken_bit = 28,
471+
.byte_clken_bit = 24,
472+
.tx_req_hsclk_bit = 31,
473+
.lane_esc_clk_bit = 19,
474+
.lane_esc_data_offset = 20,
464475
.pll_p_offset = 13,
465476
.reg_values = reg_values,
466477
.pll_fin_min = 6,
@@ -480,6 +491,11 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
480491
.wait_for_hdr_fifo = 1,
481492
.wait_for_reset = 0,
482493
.num_bits_resol = 12,
494+
.esc_clken_bit = 28,
495+
.byte_clken_bit = 24,
496+
.tx_req_hsclk_bit = 31,
497+
.lane_esc_clk_bit = 19,
498+
.lane_esc_data_offset = 20,
483499
.pll_p_offset = 13,
484500
.reg_values = exynos5433_reg_values,
485501
.pll_fin_min = 6,
@@ -499,6 +515,11 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
499515
.wait_for_hdr_fifo = 1,
500516
.wait_for_reset = 1,
501517
.num_bits_resol = 12,
518+
.esc_clken_bit = 28,
519+
.byte_clken_bit = 24,
520+
.tx_req_hsclk_bit = 31,
521+
.lane_esc_clk_bit = 19,
522+
.lane_esc_data_offset = 20,
502523
.pll_p_offset = 13,
503524
.reg_values = exynos5422_reg_values,
504525
.pll_fin_min = 6,
@@ -518,6 +539,11 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
518539
.wait_for_hdr_fifo = 1,
519540
.wait_for_reset = 0,
520541
.num_bits_resol = 12,
542+
.esc_clken_bit = 28,
543+
.byte_clken_bit = 24,
544+
.tx_req_hsclk_bit = 31,
545+
.lane_esc_clk_bit = 19,
546+
.lane_esc_data_offset = 20,
521547
/*
522548
* Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
523549
* downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
@@ -721,6 +747,7 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
721747

722748
static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
723749
{
750+
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
724751
unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
725752
unsigned long esc_div;
726753
u32 reg;
@@ -754,15 +781,17 @@ static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
754781
hs_clk, byte_clk, esc_clk);
755782

756783
reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
757-
reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
758-
| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
759-
| DSIM_BYTE_CLK_SRC_MASK);
760-
reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
761-
| DSIM_ESC_PRESCALER(esc_div)
762-
| DSIM_LANE_ESC_CLK_EN_CLK
763-
| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
764-
| DSIM_BYTE_CLK_SRC(0)
765-
| DSIM_TX_REQUEST_HSCLK;
784+
reg &= ~(DSIM_ESC_PRESCALER_MASK | BIT(driver_data->lane_esc_clk_bit)
785+
| DSIM_LANE_ESC_CLK_EN_DATA_MASK(driver_data->lane_esc_data_offset)
786+
| DSIM_PLL_BYPASS
787+
| DSIM_BYTE_CLK_SRC_MASK);
788+
reg |= BIT(driver_data->esc_clken_bit) | BIT(driver_data->byte_clken_bit)
789+
| DSIM_ESC_PRESCALER(esc_div)
790+
| BIT(driver_data->lane_esc_clk_bit)
791+
| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1,
792+
driver_data->lane_esc_data_offset)
793+
| DSIM_BYTE_CLK_SRC(0)
794+
| BIT(driver_data->tx_req_hsclk_bit);
766795
samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
767796

768797
return 0;
@@ -866,11 +895,14 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
866895

867896
static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
868897
{
898+
const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
869899
u32 reg;
870900

871901
reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
872-
reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
873-
| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
902+
reg &= ~(BIT(driver_data->lane_esc_clk_bit)
903+
| DSIM_LANE_ESC_CLK_EN_DATA_MASK(driver_data->lane_esc_data_offset)
904+
| BIT(driver_data->esc_clken_bit)
905+
| BIT(driver_data->byte_clken_bit));
874906
samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
875907

876908
reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);

‎include/drm/bridge/samsung-dsim.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,11 @@ struct samsung_dsim_driver_data {
6464
unsigned int wait_for_hdr_fifo;
6565
unsigned int wait_for_reset;
6666
unsigned int num_bits_resol;
67+
unsigned int esc_clken_bit;
68+
unsigned int byte_clken_bit;
69+
unsigned int tx_req_hsclk_bit;
70+
unsigned int lane_esc_clk_bit;
71+
unsigned int lane_esc_data_offset;
6772
unsigned int pll_p_offset;
6873
const unsigned int *reg_values;
6974
unsigned int pll_fin_min;

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