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integrate a copy of SPI from STM32F1 into STM32F4
1 parent 517e7fb commit 18b5b6e

14 files changed

Lines changed: 1549 additions & 199 deletions

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STM32F4/boards.txt

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ discovery_f407.upload.maximum_size=108000
1919
discovery_f407.build.mcu=cortex-m4
2020
discovery_f407.build.f_cpu=168000000L
2121
discovery_f407.build.core=maple
22-
discovery_f407.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -march=armv7-m -DSTM32F2 -DBOARD_discovery_f4
22+
discovery_f407.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4
2323
discovery_f407.build.ldscript=ld/jtag.ld
2424
discovery_f407.build.variant=discovery_f407
2525
discovery_f407.build.variant_system_lib=lib_f407.a
@@ -49,7 +49,7 @@ stm32f4stamp.upload.dfuse_addr=0x8000000
4949
stm32f4stamp.build.mcu=cortex-m4
5050
stm32f4stamp.build.f_cpu=168000000L
5151
stm32f4stamp.build.core=maple
52-
stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -march=armv7-m -DSTM32F2 -DBOARD_discovery_f4
52+
stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4
5353
stm32f4stamp.build.ldscript=ld/jtag.ld
5454
stm32f4stamp.build.variant=discovery_f407
5555
stm32f4stamp.build.variant_system_lib=lib_f407.a
@@ -79,7 +79,7 @@ netduino2plus.upload.dfuse_addr=0x8000000
7979
netduino2plus.build.mcu=cortex-m4
8080
netduino2plus.build.f_cpu=168000000L
8181
netduino2plus.build.core=maple
82-
netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -march=armv7-m -DSTM32F2 -DBOARD_discovery_f4
82+
netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4
8383
netduino2plus.build.ldscript=ld/jtag.ld
8484
netduino2plus.build.variant=discovery_f407
8585
netduino2plus.build.variant_system_lib=lib_f407.a

STM32F4/cores/maple/libmaple/HardwareSPI.cpp

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -65,12 +65,12 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
6565
BOARD_SPI2_MOSI_PIN},
6666
#endif
6767
#ifdef STM32_HIGH_DENSITY
68-
{BOARD_SPI3_NSS_PIN,
69-
BOARD_SPI3_SCK_PIN,
70-
BOARD_SPI3_MISO_PIN,
71-
BOARD_SPI3_MOSI_PIN},
68+
{BOARD_SPI3B_NSS_PIN,
69+
BOARD_SPI3B_SCK_PIN,
70+
BOARD_SPI3B_MISO_PIN,
71+
BOARD_SPI3B_MOSI_PIN},
7272
#endif
73-
#ifdef STM32F2
73+
#ifdef STM32F4
7474
{BOARD_SPI3B_NSS_PIN,
7575
BOARD_SPI3B_SCK_PIN,
7676
BOARD_SPI3B_MISO_PIN,
@@ -96,10 +96,10 @@ HardwareSPI::HardwareSPI(uint32 spi_num) {
9696
this->spi_d = SPI3;
9797
break;
9898
#endif
99-
#ifdef STM32F2
100-
case 4:
101-
this->spi_d = SPI4;
102-
break;
99+
#ifdef STM32F4
100+
// case 4:
101+
// this->spi_d = SPI4;
102+
// break;
103103
#endif
104104
default:
105105
ASSERT(0);
@@ -138,6 +138,15 @@ void HardwareSPI::beginSlave(void) {
138138
this->beginSlave(MSBFIRST, 0);
139139
}
140140

141+
142+
/*
143+
void HardwareSPI::beginTransaction(uint8_t pin, SPISettings settings)
144+
{
145+
// this->begin(settings.clock, settings.bitOrder, settings.dataMode);
146+
this->begin(SPI_1_125MHZ, settings.bitOrder, settings.dataMode);
147+
}
148+
*/
149+
141150
void HardwareSPI::end(void) {
142151
if (!spi_is_enabled(this->spi_d)) {
143152
return;
@@ -300,7 +309,7 @@ static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
300309
#ifdef STM32_HIGH_DENSITY
301310
case RCC_SPI3: return board_spi_pins + 2;
302311
#endif
303-
#ifdef STM32F2
312+
#ifdef STM32F4
304313
case RCC_SPI4: return board_spi_pins + 3;
305314
#endif
306315
default: return NULL;
@@ -353,7 +362,7 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
353362
disable_pwm(misoi);
354363
disable_pwm(mosii);
355364

356-
#ifdef STM32F2
365+
#ifdef STM32F4
357366
if(dev->clk_id <= RCC_SPI2) {
358367
if(nssi) {
359368
if(!as_master) {
@@ -363,9 +372,6 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
363372
gpio_set_af_mode(scki->gpio_device, scki->gpio_bit, 5);
364373
gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
365374
gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
366-
//gpio_set_af_mode(GPIOC, 10, 6);
367-
//gpio_set_af_mode(GPIOC, 11, 6);
368-
//gpio_set_af_mode(GPIOC, 12, 6);
369375
} else {
370376
if(nssi) {
371377
if(!as_master) {
@@ -375,9 +381,6 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
375381
gpio_set_af_mode(scki->gpio_device, scki->gpio_bit, 6);
376382
gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
377383
gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
378-
//gpio_set_af_mode(GPIOC, 10, 6);
379-
//gpio_set_af_mode(GPIOC, 11, 6);
380-
//gpio_set_af_mode(GPIOC, 12, 6);
381384
}
382385
#endif
383386

STM32F4/cores/maple/libmaple/HardwareSPI.h

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
#include "spi.h"
3838

3939
#include "boards.h"
40+
#include "wirish.h"
4041

4142
#ifndef _HARDWARESPI_H_
4243
#define _HARDWARESPI_H_
@@ -62,6 +63,42 @@ typedef enum SPIFrequency {
6263
//#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
6364
#endif
6465

66+
67+
//#define BOARD_SPI_DEFAULT_SS PC13
68+
#define BOARD_SPI_DEFAULT_SS PB0
69+
#define SPI_MODE0 SPI_MODE_0
70+
#define SPI_MODE1 SPI_MODE_1
71+
#define SPI_MODE2 SPI_MODE_2
72+
#define SPI_MODE3 SPI_MODE_3
73+
74+
/*
75+
class SPISettings {
76+
public:
77+
SPISettings(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
78+
if (__builtin_constant_p(clock)) {
79+
init_AlwaysInline(clock, bitOrder, dataMode);
80+
} else {
81+
init_MightInline(clock, bitOrder, dataMode);
82+
}
83+
}
84+
SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
85+
private:
86+
void init_MightInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
87+
init_AlwaysInline(clock, bitOrder, dataMode);
88+
}
89+
void init_AlwaysInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) __attribute__((__always_inline__)) {
90+
this->clock = clock;
91+
this->bitOrder = bitOrder;
92+
this->dataMode = dataMode;
93+
}
94+
uint32 clock;
95+
BitOrder bitOrder;
96+
uint8 dataMode;
97+
friend class HardwareSPI;
98+
};
99+
*/
100+
101+
65102
/**
66103
* @brief Wirish SPI interface.
67104
*
@@ -226,9 +263,17 @@ class HardwareSPI {
226263
* @see HardwareSPI::read()
227264
*/
228265
uint8 recv(void);
266+
267+
// void beginTransaction(SPISettings settings) { beginTransaction(BOARD_SPI_DEFAULT_SS, settings); }
268+
// void beginTransaction(uint8 pin, SPISettings settings);
269+
void endTransaction(void) { }
270+
229271
private:
230272
spi_dev *spi_d;
231273
};
232274

275+
276+
extern HardwareSPI SPI;
277+
233278
#endif
234279

STM32F4/cores/maple/libmaple/dma.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232

3333
#ifdef STM32F2
3434
#include "dmaF2.h"
35+
#include <libmaple/dma_common.h>
3536
#else
3637
#include "dmaF1.h"
3738
#endif
Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
/******************************************************************************
2+
* The MIT License
3+
*
4+
* Copyright (c) 2012 LeafLabs, LLC.
5+
*
6+
* Permission is hereby granted, free of charge, to any person
7+
* obtaining a copy of this software and associated documentation
8+
* files (the "Software"), to deal in the Software without
9+
* restriction, including without limitation the rights to use, copy,
10+
* modify, merge, publish, distribute, sublicense, and/or sell copies
11+
* of the Software, and to permit persons to whom the Software is
12+
* furnished to do so, subject to the following conditions:
13+
*
14+
* The above copyright notice and this permission notice shall be
15+
* included in all copies or substantial portions of the Software.
16+
*
17+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19+
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
21+
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
22+
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23+
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24+
* SOFTWARE.
25+
*****************************************************************************/
26+
27+
/**
28+
* @file libmaple/include/libmaple/dma_common.h
29+
* @author Marti Bolivar <mbolivar@leaflabs.com>
30+
* @brief Common DMA sub-header for <series/dma.h> and <libmaple/dma.h>.
31+
*
32+
* CONTENTS UNSTABLE. The existence of this file is an implementation
33+
* detail. Never include it directly. If you need something from
34+
* here, include <libmaple/dma.h> instead.
35+
*/
36+
37+
/*
38+
* There's a fair amount of common DMA functionality needed by each
39+
* <series/dma.h> and <libmaple/dma.h>. This header exists in order
40+
* to provide it to both, avoiding some hacks and circular
41+
* dependencies.
42+
*/
43+
44+
#ifndef _LIBMAPLE_DMA_COMMON_H_
45+
#define _LIBMAPLE_DMA_COMMON_H_
46+
47+
#ifdef __cplusplus
48+
extern "C"{
49+
#endif
50+
51+
#include <libmaple/libmaple_types.h>
52+
#include <libmaple/nvic.h>
53+
#include <libmaple/rcc.h>
54+
55+
/*
56+
* Devices
57+
*/
58+
59+
struct dma_reg_map;
60+
61+
/* Encapsulates state related to user interrupt handlers. You
62+
* shouldn't touch these directly; use dma_attach_interrupt() and
63+
* dma_detach_interupt() instead. */
64+
//typedef struct dma_handler_config {
65+
// void (*handler)(void); /* User handler */
66+
// nvic_irq_num irq_line; /* IRQ line for interrupt */
67+
//} dma_handler_config;
68+
69+
/** DMA device type */
70+
//typedef struct dma_dev {
71+
// struct dma_reg_map *regs; /**< Register map */
72+
// rcc_clk_id clk_id; /**< Clock ID */
73+
// struct dma_handler_config handlers[]; /**< For internal use */
74+
//} dma_dev;
75+
76+
/**
77+
* @brief DMA channels
78+
*
79+
* Notes:
80+
* - This is also the dma_tube type for STM32F1.
81+
* - Channel 0 is not available on all STM32 series.
82+
*
83+
* @see dma_tube
84+
*/
85+
typedef enum dma_channel {
86+
DMA_CH0 = 0, /**< Channel 0 */
87+
DMA_CH1 = 1, /**< Channel 1 */
88+
DMA_CH2 = 2, /**< Channel 2 */
89+
DMA_CH3 = 3, /**< Channel 3 */
90+
DMA_CH4 = 4, /**< Channel 4 */
91+
DMA_CH5 = 5, /**< Channel 5 */
92+
DMA_CH6 = 6, /**< Channel 6 */
93+
DMA_CH7 = 7, /**< Channel 7 */
94+
} dma_channel;
95+
96+
/**
97+
* @brief Source and destination transfer sizes.
98+
* Use these when initializing a struct dma_tube_config.
99+
* @see struct dma_tube_config
100+
* @see dma_tube_cfg
101+
*/
102+
//typedef enum dma_xfer_size {
103+
// DMA_SIZE_8BITS = 0, /**< 8-bit transfers */
104+
// DMA_SIZE_16BITS = 1, /**< 16-bit transfers */
105+
// DMA_SIZE_32BITS = 2, /**< 32-bit transfers */
106+
//} dma_xfer_size;
107+
108+
#ifdef __cplusplus
109+
} // extern "C"
110+
#endif
111+
112+
#endif

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