@@ -86,9 +86,23 @@ extern const struct adc_dev *ADC3;
8686#define ADC_CR2_RSTCAL (1U << ADC_CR2_RSTCAL_BIT)
8787#define ADC_CR2_DMA (1U << ADC_CR2_DMA_BIT)
8888#define ADC_CR2_ALIGN (1U << ADC_CR2_ALIGN_BIT)
89- #define ADC_CR2_JEXTSEL 0x7000
89+ #define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
90+ #define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
91+ #define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
92+ #define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
93+ #define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
94+ #define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
95+ #define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
96+ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12)
9097#define ADC_CR2_JEXTTRIG (1U << ADC_CR2_JEXTTRIG_BIT)
91- #define ADC_CR2_EXTSEL 0xE0000
98+ #define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
99+ #define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
100+ #define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
101+ #define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
102+ #define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
103+ #define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
104+ #define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
105+ #define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
92106#define ADC_CR2_EXTTRIG (1U << ADC_CR2_EXTTRIG_BIT)
93107#define ADC_CR2_JSWSTART (1U << ADC_CR2_JSWSTART_BIT)
94108#define ADC_CR2_SWSTART (1U << ADC_CR2_SWSTART_BIT)
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